本文利用台積電0.35μm 2P4M標準積體電路代工（CMOS foundry）和後製程程序（post process），製作壓力感測薄膜為50μm×50μm大小之壓阻式壓力感測器；壓力薄膜之材質為二氧化矽，壓電阻之材質為多晶矽。因應微小壓力薄膜之製作，本文利用正面濕式蝕刻的方式進行中空壓力腔之後製程，蝕刻孔洞大小為5μm×5μm。在濕式蝕刻製程中，預先設計之金屬犧牲層將被蝕去，得到感測薄膜之微結構，其後利用氫氧化鉀(KOH)對矽基底材蝕刻出V型槽(V-groove)，為得到與外界隔絕之壓力感測器之空腔結構，此處使用明膠(gelatin)來進行孔洞填塞，最後對晶片進行加壓測試。
加壓測試結果顯示，在壓力感測器的驅動電壓為1伏特，壓力量測範圍0~60psi之下，本壓力感測器之靈敏度為8.56±0.13 mv/v/psi，線性度4.3±1.6%，遲滯度小於1%。本文利用CMOS微機電製程製作壓阻式壓力感測器，並配合後製程和明膠封裝技術製作薄膜微結構，具面積小、靈敏度高之特性。

This work investigates the fabrication of a piezoresistive micro pressure sensor with the size of 50μm×50μm using the standard CMOS and post process. The CMOS foundry, TSMC 0.35μm 2P4M process herein, is provided by CIC (Chip Implementation Center), Taiwan. The material of sensor membrane is silicon dioxide, and piezoresistors are made by polysilicon. To release the membranes of micro pressure sensors, this work proposes to use the front-side etching technique with etching holes of 5μm×5μm only. In wet etching process, the sacrificial metal layers will be removed, and release the membrane structure. After these, the V-grooves are etched anisotropically into the silicon substrate using KOH, and to get the pressure sensor's cavity which is separated from the outside. Here we use one of the protein stuffs, gelatin, to seal the etching holes, and examine the chip in pressure test.  
In the pressure test, the operating bias voltage of pressure sensor is 1 Volt, and the testing pressure ranges from 0 to 60psi. The performance of pressure sensor, the sensitivity is around 8.56±0.13 mv/v/psi, the linearity is 4.3±1.6%, and the hysteresis is less than 1%. This work demonstrated a piezoresistive pressure sensor which was made by CMOS MEMS technique, post process, and the packaging of gelatin. With the electrical/mechanical integration the micro structure of membrane , the  micro force sensor have the advantages of smaller size and high sensitivity.

目錄
誌謝
中文摘要………………………………….………………………...Ⅰ
英文摘要………………………………….………………………...Ⅱ
目錄………………………………….………………………...……Ⅳ
圖目錄………………………………….………………………...…Ⅵ
表目錄………………………………………..…………………..…Ⅸ
第一章  緒論…………………………………………….………….1
1-1 研究動機………………………………….……….…1
1-2 研究目的…………………………………..…………3
1-3 文獻回顧………………………………………..……4
1-4 章節提要………………………………………..……6
第二章  CMOS MEMS技術………………………….……………7
2-1 標準CMOS製程簡介…………………….…………7
2-2 CMOS後製程處理程序…………………………...…8
2-3 全客戶式IC設計………………………………….…9
2-4 CMOS微機電元件之研發流程………………......…10
第三章  CMOS壓力感測晶片設計原理……………………….......14
3-1 CMOS壓阻式壓力感測器之設計流程圖………..….14
3-2 CMOS 2P4M製程結構說明……………………........15
3-3 壓力感測晶片之感測原理………………..….…...…15
3-4 壓力感測薄膜模擬分析……………………….….…17
3-5 晶片正面蝕刻法與蝕刻孔設計…………………..…19
3-6 壓力感測晶片佈局設計…………………………..…20
第四章  CMOS壓力感測晶片後製程及量測……………...…...…29
4-1 CMOS MEMS後製程蝕刻法………………….….…29
4-2 濕式蝕刻流程………………………………..………29
4-3 壓力感測晶片封裝…………………………..………32
4-4 壓力感測晶片量測……………………………..……34
4-4-1 量測設備………………………………………34
4-4-2 量測方式………………………………………35
第五章  實驗結果與討論………………………………….……….37
5-1 濕式蝕刻結果與討論………………………….……37
5-2 壓力感測晶片封裝結果與討論…………….………42
5-3 壓力感測晶片量測結果與討論………………….…44
第六章  結論與建議………………………………………..………49
6-1 結論…………………………………………..………49
6-2 建議………………………………………………..…50
參考文獻……………………………………………………………...53

圖目錄
圖2-1 典型的CMOS剖圖……………………..………………..……8
圖2-2 全客戶式設計流程(Full-Custom Design Flow)…...……..…...10
圖2-3 CMOS微機電元件之研發流程…...………………………..…11
圖3-1 CMOS壓阻式壓力感測器之設計流程圖…………….………14
圖3-2 CMOS 0.35um 2P4M標準製程結構示意圖………………….15
圖3-3 惠斯登電橋………………………………………………....….16
圖3-4 壓電阻佈置圖……………………………………………….…16
圖3-5 壓電阻受力圖………………………………………………….16
圖3-6 壓力感測薄膜結構三維立體模型……………………….….....17
圖3-7 紅色區塊為薄膜在X軸向應力集中之位置……………….…18
圖3-8 紅色區塊為薄膜在Y軸向應力集中之位置……………….…18
圖3-9 薄膜變形模擬圖…………………………………………..……19
圖3-10 背面蝕刻示意圖…………………………………………..…..20
圖3-11 正面蝕刻示意圖……………………………………………….20
圖3-12 於Cadence工作站中繪製晶片佈局圖……………………….22
圖3-13 單一壓力感測元件之晶片佈局圖…………………………....22
圖3-14 本文壓力感測晶片剖面示意圖..…...…………………...……23
圖3-15 經濕蝕刻所得之壓力薄膜示意圖......……………………..…23
圖3-16 (a)以光學顯微鏡(以下簡稱OM)拍攝之上視圖；(b)以掃描式電
       子顯微鏡(以下簡稱SEM)拍攝之上視圖；(c)以SEM拍攝之側
       視圖；(d)以SEM拍攝之側視圖………..……………...……24 
圖3-17 壓力感測元件陣列之晶片佈局圖……………………………24
圖3-18 使用metal-1 layer連接各感測元件之佈局圖.………….……25
圖3-19 使用metal-2 layer連接到pad之佈局圖………..………….…25
圖3-20 使用metal-3 layer連接到pad之佈局圖………………...……25
圖3-21 多晶矽(poly-silicon)之佈局圖……………………..….………27
圖3-22 灌孔層(contact)之佈局圖……………………….…….………27
圖3-23 金屬層(metal-1)之佈局圖…………………………….………27
圖3-24 灌孔層(via12)之佈局圖……………………………….………27
圖3-25 金屬層(metal-2)之佈局圖…………………………….….……28
圖3-26 灌孔層(via23)之佈局圖……………………………….………28
圖3-27 金屬層(metal-3)之佈局圖………………………………..……28
圖3-28 灌孔層(via34)之佈局圖……………………………….………28
圖3-29 金屬層(metal-4)之佈局圖………………………………..……28
圖3-30 保護層(passivation)之佈局圖…………………………………28
圖4-1 CMOS(2P4M)壓力感測器MEMS後製程流程…………..……30
圖4-2 濕式蝕刻的實驗設備……………………………...….…..……31
圖4-3 壓力測試機台…………………………………………….……35
圖4-4 數據擷取機……………………………………………….……35
圖4-5 設備連接示意圖………………………………………….……35
圖4-6 壓力感測器與電訊號線之連接………………………….……36
圖5-1 未經任何加工之晶片全貌圖(OM拍攝) ………………..……37
圖5-2 經KOH蝕刻後的晶片全貌圖(OM拍攝) ……………...……37
圖5-3 以OM拍攝之晶片上視圖…………………………....….……38
圖5-4 以OM往下對焦，而直接拍攝到倒金字塔型之軌跡….……38
圖5-5 探針…………………………………………………....…..……38
圖5-6 探針台…………………………………………………......……38
圖5-7 探針台之實驗設備全貌……………………………...…...……39
圖5-8 以SEM拍攝壓力薄膜微結構..……………………...……...…40
圖5-9 刺破的壓力薄膜後，以α-step作表面形貌的量測…..………41
圖5-10 晶片打線之圖片(OM拍攝) …………………………..………43
圖5-11 晶片黑膠封裝之圖片………………………………….………43
圖5-12 明膠封裝(OM拍攝)……………………………...…………...43
圖5-13 晶片封裝完成圖………………………………………………44
圖5-14 CMOS壓力感測晶片第一次量測結果………………………45
圖5-15 CMOS壓力感測晶片第二次量測結果………………....……46
圖5-16 CMOS壓力感測晶片第三次量測結果………………………46

表目錄
表4-1 三種濕式蝕刻液之調配比例………………………...........…30
表5-1 CMOS壓力感測器之性能比較………………………..…..…48
表5-2 CMOS壓力感測器之尺寸與輸出特性………………...…….48

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