本論文提出一種雙足行走步態的設計方式，並用座標旋轉數位計算器（CORDIC）演算法將行走步態和逆運動學計算利用SOPC方式實現。在行走步態方面，本論文在基於振盪為基礎的簡單模型中，提出一些可以利用正弦函數來描述雙足行走步態的公式。為了更自然更容易定義所描述的振盪器參數，本論文選擇以機器人的腰部擺動長度、步伐長度、抬腳高度以及行走時間作為參數設定，可針對機器人特性與需求各別設定，不需要精確的數學模型，即可輕易地設計所需的步態軌跡，再利用逆運動學求得步態軌跡與各馬達間的關係。由於CORDIC只需要加減法、位移及少數的記憶體即可實現根號、三角與反三角等函數的計算，所以本論文以CORDIC演算法來實現機器人之步態軌跡和逆運動學的函數計算。由實驗結果得知，借由FPGA硬體電路高速平行運算的特性，可以大幅降低IPC工業電腦與Nios II軟體執行的運算負擔，也讓IPC與Nios II較有餘力執行影像、策略以及智慧型演算法等功能。以FPGA硬體電路實現機器人的行走步態系統和逆運動學，其計算只產生小範圍的誤差。因此，本論文以CORDIC演算法將機器人步態軌跡和逆運動學利用SOPC方式實現可以達到即時控制，最後再加上利用FPGA方式實現機器人行走之地面傾斜估測方式來判斷是否行走在傾斜地面。

In this thesis, a design method of biped gait for humanoid robots is proposed.
A CORDIC-based SOPC system is used to design biped gait and inverse
kinematics. In the biped gait, some equations represented by sinusoidal
functions are proposed to describe a biped walking. In order to be more
natural and of more practical importance, oscillation parameters are described
by the swing length, step length, and lifting height of a biped robot. These
parameters can be set from characteristics and requirements for biped robot.
Accurate mathematics model is not necessary. The biped gait can be easily
designed. Then we use inverse kinematics to obtain the relationship between
gait trajectory and each motor. Because CORDIC algorithm only needs
addition and subtraction, displacement, and mininal memory for calculating
the square-root, trigonometric, and inverse trigonometric functions, thus the
CORDIC algorithm method is used to calculate walking gait and inverse
kinematics for a biped robot in this paper. From the experimental results,
FPGAs are capable of high- performance parallel computing, the
computational burden of IPC and Nios II soft-core processor can be greatly
reduced. Let master controller can execute strategic, image processing,
intelligent algorithms , etc. FPGA hardware method is used to compute the
walking gait and inverse kinematics. These results computed by the FPGA
hardware method are almost the same as that computed by the software
method. Therefore, the proposed CORDIC-based FPGA hardware design
method can really be applied to improve the real-time control performance of
biped robot. And a estimation method of a walking robot on a horizontal plane
is designed on the FPGA hardware method to determine whether the robot can
working in slope surface

目錄	I
圖目錄	IV
表目錄	VIII
第一章　緒論	1
1.1　研究背景	1
1.2　研究動機	3
1.3　研究目的	3
1.4　論文架構	4
第二章　座標旋轉數位計算器	5
2.1　前言	5
2.2　兩種計算模式	6
2.3　三種座標系統	10
2.4　廣義表示法	12
2.5　實驗結果	18
第三章　人形機器人步態軌跡之FPGA設計	22
3.1　前言	22
3.2　步態軌跡	23
3.3　FPGA硬體電路設計	34
3.4　實驗結果	39
第四章　人形機器人逆運動學之FPGA設計	43
4.1　前言	43
4.2　逆運動學	44
4.3　FPGA硬體電路設計	49
4.4　實驗結果	52
第五章　人形機器人即時行走之SOPC設計	57
5.1　前言	57
5.2　人形機器人系統	58
5.3　SOPC設計	61
5.4　實驗結果	65
第六章　行走地面傾斜估測之FPGA設計	72
6.1　前言	72
6.2　加速度計	73
6.3　行走地面傾斜估測	77
6.4　FPGA設計	82
6.5　實驗結果	83
第七章　結論與未來展望	85
7.1　結論	85
7.2　未來展望	85
參考文獻	87
研究著作	92
期刊論文	92
會議論文	92
專利	93
學位論文	93
獲獎經歷	94


圖2.1、旋轉模式之座標軸旋轉示意圖	7
圖2.2、向量模式之向量旋轉示意圖	9
圖2.3、實現CORDIC演算法基本模組之架構圖：(a) cr模組、(b) lr模組、(c) cv模組和(d) hv模組	16
圖2.4、函數計算模組之輸出入關係圖：(a)正弦函數、(b)反正切函數、(c)兩數平方和之平方根和(d)兩數平方差之平方根	17
圖2.5、函數計算模組之表示方式：(a)正弦函數、(b)反正切函數、(c)兩數平方和之平方根和(d)兩數平方差之平方根	18
圖2.6、函數計算模組計算(虛線)與實際數值(實線)結果：(a)正弦函數、(b)反正切函數、(c)兩數平方和之平方根和(d)兩數平方差之平方根	20
圖2.7、函數計算模組之誤差：(a)正弦函數、(b)反正切函數、(c)兩數平方和之平方根和(d)兩數平方差之平方根	21
圖3.1、腰部及腳部軌跡示意圖	24
圖3.2、雙足機器人示意圖	24
圖3.3、雙足機器人站立示意圖：(a)正視圖、(b)右方側視圖和(c)上視圖	25
圖3.4、完整行走步態示意圖：(a)正視圖、(b)右方側視圖和(c)上視圖	27
圖3.5、腰部的運動軌跡示意圖：(a)上視圖、(b)開始模式之正視圖、(c)連續模式之正視圖和(d)結束模式之正視圖	29
圖3.6、雙足踝關節的運動軌跡的側視示意圖：(a)右腳踝關節和(b)左腳踝關節	29
圖3.7、雙足機器人之一個完整行走過程的擺動位置模擬圖：(a)腰部、(b)右腳踝關節、(c)左腳踝關節和(d)3D運動軌跡	32
圖3.8、雙足機器人之一個完整行走過程的擺動位置模擬圖：(a)右腳髖關節和(b)左腳髖關節	33
圖3.9、完整行走過程之計算結果模擬圖：(a) LR和(b) LL	34
圖3.10、雙足行走步態設計之FPGA硬體電路架構圖	35
圖3.11、Waist Osc模組和Ankle Osc模組之FPGA硬體電路架構圖：(a)Waist Osc模組、(b)右腳Ankle Osc模組和(c)左腳Ankle Osc模組	35
圖3.12、Osc模組之FPGA硬體電路架構圖	36
圖3.13、基於CORDIC運算之CR模組的FPGA硬體電路架構圖	36
圖3.14、FPGA硬體電路架構圖：(a)Add模組和(b)Sub模組	37
圖3.15、Nios II軟體執行(實線)與FPGA硬體電路(圓點)計算結果：(a) LR和(b) LL	40
圖3.16、Nios II軟體執行與FPGA硬體電路計算誤差：(a) LR和(b) LL	41
圖4.1、雙足機器人的座標軸示意圖：(a)正視圖和(b)右方側視圖	45
圖4.2、完整行走過程之關節轉動模擬圖：(a)右腳和(b)左腳	47
圖4.3、完整行走過程之3D模擬圖：(a) t = 0秒(站立動作)、(b) t = 0.5秒(動作1)、(c) t = 0.75秒(動作2)、(d) t = 1.5秒(動作3)、(e) t = 2.5秒(動作4)、(f) t = 3.5秒(動作3)、(g) t = 4.5秒(動作4)、(h) t = 5秒(動作5)、(i) t = 5.5秒(動作6)和(j) t = 6秒(站立動作)	49
圖4.4、雙足行走步態之FPGA硬體電路架構圖	50
圖4.5、逆運動學模組之FPGA硬體電路架構圖	50
圖4.6、Single Leg IK模組之FPGA硬體電路架構圖	51
圖4.7、Nios II軟體執行(實線)與FPGA硬體電路(圓點)計算結果：(a)右腳和(b)左腳	53
圖4.8、Nios II軟體執行與FPGA硬體電路計算誤差：(a)右腳和(b)左腳	54
圖5.1、第九代小型人形機器人：(a)模擬圖和(b)實體圖	58
圖5.2、第九代小型人形機器人尺寸：(a)正面和(b)側面	59
圖5.3、IPC工業電腦實體圖：(a)正面和(b)反面	59
圖5.4、FPGA開發板實體圖：(a)正面和(b)反面	60
圖5.5、即時行走之系統方塊圖	62
圖5.6、步態軌跡模組之FPGA硬體電路架構圖	63
圖5.7、Waist CR模組和Ankle CR模組之FPGA硬體電路架構圖：(a)Waist CR模組、(b)右腳Ankle CR模組和(c)左腳Ankle CR模組	64
圖5.8、基於CORDIC運算之CR模組的FPGA硬體電路架構圖	64
圖5.9、實驗一之小型人形機器人即時行走結果：(a) 45°視角、(b)右方側視角和(c)正面視角	68
圖5.10、實驗二之小型人形機器人即時行走結果：(a) 45°視角、(b)右方側視角和(c)正面視角	71
圖6.1、加速度計座標軸	73
圖6.2、加速度計實體圖：(a)正面和(b)反面	74
圖6.3、靜置不動的加速度計y軸數值：(a)量測的加速度和(b) 2次積分後的位置	75
圖6.4、機器人步行時身體的擺動軌跡	75
圖6.5、機器人踏步模擬平台：(a)模擬圖和(b)實體圖	76
圖6.6、使用機器人踏步模擬平台時對y軸擺動：(a) 擺動軌跡、(b)量測的加速度和(c) 2次積分後的位置	76
圖6.7、透過快速傅立葉訊號分析：(a)原始訊號和(b)頻率分析	78
圖6.8、一階巴特沃斯低通濾波器濾波後的結果	79
圖6.9、可自由改變傾斜角度之傾斜裝置：(a)模擬圖和(b)實體圖	79
圖6.10、機器人踏步模擬平台放置在傾斜裝置上：(a)設定為水平、(b)右上左下傾斜7o和(c)右下左上傾斜7o	80
圖6.11、右上左下傾斜7o之加速度計訊號：(a)原始訊號和(b)濾波後結果	80
圖6.12、濾波結果與擺動週期的算數平均值	81
圖6.13、右下左上傾斜7o之加速度計訊號：(a)原始訊號和(b)濾波結果與擺動週期的算數s平均值	81
圖6.14、小型人形機器人行走姿態估測之系統方塊圖	82
圖6.15、姿態估測之BW模組的FPGA硬體電路架構圖	82
圖6.16、姿態估測之Mean模組的FPGA硬體電路架構圖	83
圖6.17、小型人形機器人在水平面踏步之加速度計訊號：(a)原始訊號和(b)濾波結果與擺動週期的算數平均值	84
圖6.18、小型人形機器人放置在右上左下傾斜踏步之加速度計訊號：(a)原始訊號和(b)濾波結果與擺動週期的算數平均值	84


表2.1、CORDIC演算法基本運算之輸出入關係表	14
表2.2、座標系統參數m、疊代運算序列i和Km之關係表	14
表2.3、CORDIC演算法疊代運算參數表	15
表2.4、函數計算模組所使用之邏輯單元	19
表2.5、函數計算模組之可計算數值範圍	19
表2.6、FPGA硬體電路實現函數計算模組之計算效能	21
表3.1、機器人行走步態之開始模式的振盪器參數表	30
表3.2、機器人行走步態之連續模式的振盪器參數表	31
表3.3、機器人行走步態之結束模式的振盪器參數表	31
表3.4、機器人行走步態參數表	32
表3.5、Osc模組的計算步驟	36
表3.6、Waist Osc模組之Osc模組的輸出入變數對照表	36
表3.7、Ankle Osc模組之Osc模組的輸出入變數對照表	37
表3.8、Add模組的計算步驟	38
表3.9、Sub模組的計算步驟	38
表3.10、Add模組的輸出入變數對照表	38
表3.11、Sub模組的輸出入變數對照表	39
表3.12、各程式模組使用邏輯單元和晶片容量對照表	39
表3.13、Nios II軟體執行與FPGA硬體電路計算LR和LL誤差範圍	41
表3.14、FPGA硬體電路實現所須執行的時脈週期數目	41
表3.15、Nios II軟體執行與FPGA硬體電路單次執行速度	41
表4.1、Single Leg IK模組之計算步驟	51
表4.2、Single Leg IK模組之輸出入變數對照表	52
表4.3、各程式模組使用邏輯單元和晶片容量對照表	52
表4.4、Nios II軟體執行與FPGA硬體電路計算誤差範圍	55
表4.5、FPGA硬體電路實現所須執行的時脈週期數目	55
表4.6、Nios II軟體執行與FPGA硬體電路單次執行速度	55
表5.1、IPC工業電腦之系統規格	60
表5.2、FPGA開發板之系統規格	61
表5.3、Waist CR模組之CR模組的輸出入變數對照表	64
表5.4、Ankle CR模組之CR模組的輸出入變數對照表	65
表5.5、FPGA硬體電路實現所須執行的時脈週期數目	65
表5.6、Nios II軟體執行與FPGA硬體電路單次執行速度	66
表5.7、實驗一之機器人行走步態參數表	66
表5.8、實驗二之機器人行走步態參數表	69

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