淡江大學覺生紀念圖書館 (TKU Library)
進階搜尋


下載電子全文限經由淡江IP使用) 
系統識別號 U0002-0808201212030900
中文論文名稱 更佳的遮罩測試響應的未知值
英文論文名稱 Optimal Unknown Bit Filtering for Test Response Masking
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 100
學期 2
出版年 101
研究生中文姓名 翁定克
研究生英文姓名 Ding-Ke Weong
學號 699450051
學位類別 碩士
語文別 英文
口試日期 2012-06-13
論文頁數 38頁
口試委員 指導教授-饒建奇
委員-梁新聰
委員-陳竹一
中文關鍵字 測試響應  遮罩未知值  壓縮器 
英文關鍵字 test response  X-masking  compaction 
學科別分類 學科別應用科學電機及電子
中文摘要 IC測試發展至今,在LFDR與MISR已經能提供很高的壓縮率,不幸的是測試輸出有未知值(X)混在裡面,導致壓縮器的輸出信號失去可靠性。很多的研究加入X遮罩邏輯(XML)連接在測試響應(test response)與壓縮器 (compactor)之間,由於簡單的反饋電路防止X狀態擴散。但X遮罩邏輯(XML)必須加入額外的控制碼,這樣使得效率難以提高。
本篇文章所提出的行列XML是一個新型的組合電路。我們的方法能阻斷X傳遞,且用較少的控制碼,但是產生控制碼不像XML這麼直接,因此同時提出產生控制碼的演算方法,能夠有效地遮罩X且觀察到較多的錯誤(fault),最後,在我們最好的實驗結果,優於XML壓縮率達6.65%。
英文摘要 With developments of IC testing, LFSR and MISR technologies provide very high compression rate. However, unknown (X) states which decrease the reliability are injected into compactor. Many researches added the X-masking logic (XML) which connects between test response and compactor and prevents multiplication of X states due to their simple feedback circuitry. Further, the XML needs to add extra control codes which make it difficult to improve the efficiency.
This thesis proposed the method, row-column XML, which is a novel combinational circuit. Our method can block the propagation of X and also use less control codes, but it cannot direct generate control codes as XML. So we also provided the generation algorithm of control code which can mask X efficiently and observe more testing faults. Finally, in best case, our experimental results obtains better compression rate than XML about 6.65%.
論文目次 TABLE OF CONTENTS
中文摘要 I
英文摘要 II
TABLE OF CONTENTS III
List of Figures V
List of Tables VI

CHAPTER 1 INTORDUCTION 1
1.1 Movtivation 4
1.2 Thesis Overview 5

CHAPTER 2 BASIC CONCEPTS 6
2.1 Fault Model 6
2.2 Design For Testability 8
2.3 Output Response Analyzer 10
2.4 Compactor 10
2.4.1Space Compactor 11
2.4.2Time Compactor 12
2.5X-Masking 14

CHAPTER 3 PROPOSED ARCHITECTURE AND TECHNOLOG 16
3.1 Row-Column XML Architecture 16
3.2 Generate Mask Code 17
3.2.1 Greedy Algorithm 19
3.2.2 Expectation Algorithm 20
3.2.2.1 Formula Origin 20
3.2.2.2 Execution Procedure 22
3.2.2.3 Example 23
3.2.2.4 Simplify 25
3.2.2.5 Optimization 25
3.3 FAULT COVERAGE 26
3.3.1 Recover Fault Coverage 26
3.3.2 Focus Specific Fault Control Patterns 27
CHAPTER 4 EXPERIMENTAL RESULTS 31
CHAPTER 5 CONCLUSIONS 36

Reference 37

LIST OF FIGURES

Figure 1.1 EDT architecture 2
Figure 2.1 XOR fault free and faulty 7
Figure 2.2 Fault simulation of determine circuit isn’t correct 8
Figure 2.3 Transforming a sequential circuit for scan design 9
Figure 2.4 Cycle operation in scan design 10
Figure 2.5 X-compact matrices and corresponding response compaction circuits 12
Figure 2.6 A MISR with n registers 13
Figure 2.7 A MISR example. The initial MISR state is 0000 13
Figure 2.8 X-masking logic 15
Figure 3.1 Row-column XML architecture 16
Figure 3.2 Scan chain implemented mask in Row-column XML 17
Figure 3.3 Fault effects captured in flip-flops 18
Figure 3.4 Weight Matrix transferred from Fault effects in flip-flops 18
Figure 3.5 The result of same test pattern with two kinds of mask 19
Figure 3.6 A matrix sample 21
Figure 3.7 Matrix of changes when calculating mask code 24
Figure 3.8 A result of added value G after mask calculation, gray part are behalf of to be masked 27
Figure 3.9 Modification of row-column XML architecture 28
Figure 3.10 Each fault list of changes after fault simulation in every pattern 29
Figure 3.11 Flow diagram 30

LIST OF TABLES

Table 2.1 MISR states in every clock cycle 14
Table 2.2 X-masking Input-output relationship 15
Table 4.1 Exhaustive algorithm in row-column XML architecture 32
Table 4.2 Greedy algorithm in row-column XML architecture 32
Table 4.3 Expectation algorithm in row-column XML architecture 34
Table 4.4 Exhaustive algorithm with focus specific fault control pattern 34
Table 4.5 Expectation algorithm with focus specific fault control pattern 34
參考文獻 [1] W. Rajski and J. Rajski, “Modular compactor of test responses,” Proc. VTS, pp. 242-251, 2006.
[2] S. Mitra and K. S. Kim, “X-Compact: an efficient response compaction technique,” IEEE Trans. CAD, vol. 23, pp. 421- 432, March 2004.
[3] J. H. Patel, S. S. Lumetta, and S. M. Reddy, “Application of Saluja-Karpovsky compactors to test responses with many unknowns,” Proc. VTS, pp. 107-112, 2003.
[4] T. Clouqueur, H. Fujiwara, K. Zarrineh, and K. Saluja, “Design and analysis of multiple-weight linear compactors of responses containing unknown values,” Proc. ITC, pp. 1099-1108, 2005.
[5] J. Rajski, J. Tyszer, C. Wang, and S. Reddy, “Convolutional compaction of test responses,” Proc. ITC, pp.745-754, 2003.
[6] C. Wang, et al., “On compacting test responses data containing unknown values,” Proc. ICCAD, pp. 855-862, 2003.
[7] C. Barnhart, et al., “OPMISR: The foundation for compressed ATPG vectors,” Proc. ITC, pp. 748-757, 2001.
[8] J. Rajski, et al., “Embedded deterministic test for low cost manufacturing test,” Proc. ITC, pp. 301-310, 2002.
[9] H. Tang, et al., “On efficient X-handling using a selective compaction scheme to achieve high test response compaction ratios”, Proc. VLSI Design, pp. 59-64, 2005.
[10] M. Naruse, I. Pomeranz, S.M. Reddy, and S. Kundu, “On chip compression of output responses with unknown values using LFSR reseeding,” Proc. ITC, pp. 1060-1068, 2003.
[11] S. Wang, K.J. Balakrishnan, and W. Wei, “X-Block: An efficient LFSR reseeding-based method to block unknowns for temporal compactors,” IEEE Trans. Comput, vol. 57, pp. 978-989, July 2008.
[12] S. Wang, W. Wei, and S.T. Chakradhar, “Unknown blocking scheme for low control data volume and high observability,” Proc. DATE, pp. 1 – 6, 2007.
[13] E.H. Volkerink and S. Mitra, “Response compaction with any number of unknowns using a new LFSR architecture,” Proc.DAC, pp. 117-122, 2005.
[14] P. Wohl, J.A. Waicukauski, S. Patel, and A. Amin, “X-tolerant compression and application of scan-ATPG patterns in a BIST architecture,” Proc. ITC, pp. 727-736, 2003.
[15] Y. Tang, et al., “X-masking during logic BIST and its impact on defect coverage,” Proc. ITC, pp. 442-451, 2003.
[16] I. Pomeranz, S. Kundu, and S. M. Reddy, “On output response compression in the presence of unknown output values,”Proc. DAC, pp. 255-258, 2002.
[17] V. Chickermane, B. Foutz, and B. Keller, “Channel masking synthesis for efficient on-chip test compression,” Proc. ITC,pp. 452-461, 2004.
[18] S. Mitra, S.S. Lumetta, M. Mitzenmacher, “X-tolerant signature analysis,” Proc. ITC, pp. 432-441, 2004.
[19] Sinanoglu, O.; Almukhaizim, S, “X-Align: Improving the Scan Cell Observability of Response Compactors,” IEEE Trans. Comput, vol. 17, pp.1392 – 1404, 2009.
[20] Chao, M.C.-T. ; Seongmoon Wang ; Chakradhar, S.T. ; Kwang-Ting Cheng, “Response shaper: a novel technique to enhance unknown tolerance for output response compaction,” Proc. ICCAD, pp. 80 – 87, Nov. 2005.
[21] By Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng “Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon)” Pub. Morgan Kaufmann, 2009
論文使用權限
  • 同意紙本無償授權給館內讀者為學術之目的重製使用,於2012-08-13公開。
  • 同意授權瀏覽/列印電子全文服務,於2012-08-13起公開。


  • 若您有任何疑問,請與我們聯絡!
    圖書館: 請來電 (02)2621-5656 轉 2281 或 來信