IC測試發展至今，在LFDR與MISR已經能提供很高的壓縮率，不幸的是測試輸出有未知值(X)混在裡面，導致壓縮器的輸出信號失去可靠性。很多的研究加入X遮罩邏輯(XML)連接在測試響應(test response)與壓縮器 (compactor)之間，由於簡單的反饋電路防止X狀態擴散。但X遮罩邏輯(XML)必須加入額外的控制碼，這樣使得效率難以提高。
本篇文章所提出的行列XML是一個新型的組合電路。我們的方法能阻斷X傳遞，且用較少的控制碼，但是產生控制碼不像XML這麼直接，因此同時提出產生控制碼的演算方法，能夠有效地遮罩X且觀察到較多的錯誤(fault)，最後，在我們最好的實驗結果，優於XML壓縮率達6.65%。

With developments of IC testing, LFSR and MISR technologies provide very high compression rate. However, unknown (X) states which decrease the reliability are injected into compactor. Many researches added the X-masking logic (XML) which connects between test response and compactor and prevents multiplication of X states due to their simple feedback circuitry. Further, the XML needs to add extra control codes which make it difficult to improve the efficiency.
This thesis proposed the method, row-column XML, which is a novel combinational circuit. Our method can block the propagation of X and also use less control codes, but it cannot direct generate control codes as XML. So we also provided the generation algorithm of control code which can mask X efficiently and observe more testing faults. Finally, in best case, our experimental results obtains better compression rate than XML about 6.65%.

TABLE OF CONTENTS
中文摘要	I
英文摘要	II
TABLE OF CONTENTS	III
List of Figures	V
List of Tables	VI

CHAPTER 1 INTORDUCTION	1
1.1 Movtivation	4
1.2 Thesis Overview	5

CHAPTER 2 BASIC CONCEPTS	6
2.1 Fault Model	6
2.2 Design For Testability	8
2.3 Output Response Analyzer	10
2.4 Compactor	10
2.4.1Space Compactor	11
2.4.2Time Compactor	12
2.5X-Masking	14

CHAPTER 3 PROPOSED ARCHITECTURE AND TECHNOLOG	16
3.1 Row-Column XML Architecture	16
3.2 Generate Mask Code	17
3.2.1 Greedy Algorithm	19
3.2.2 Expectation Algorithm	20
3.2.2.1 Formula Origin	20
3.2.2.2 Execution Procedure	22
3.2.2.3 Example	23
3.2.2.4 Simplify	25
3.2.2.5 Optimization	25
3.3 FAULT COVERAGE	26
3.3.1 Recover Fault Coverage	26
3.3.2 Focus Specific Fault Control Patterns	27
CHAPTER 4 EXPERIMENTAL RESULTS	31
CHAPTER 5 CONCLUSIONS	36

Reference	37

LIST OF FIGURES

Figure 1.1 EDT architecture	2
Figure 2.1 XOR fault free and faulty	7
Figure 2.2 Fault simulation of determine circuit isn’t correct	8
Figure 2.3 Transforming a sequential circuit for scan design	9
Figure 2.4 Cycle operation in scan design	10
Figure 2.5 X-compact matrices and corresponding response compaction circuits	12
Figure 2.6 A MISR with n registers	13
Figure 2.7 A MISR example. The initial MISR state is 0000	13
Figure 2.8 X-masking logic	15
Figure 3.1 Row-column XML architecture	16
Figure 3.2 Scan chain implemented mask in Row-column XML	17
Figure 3.3 Fault effects captured in flip-flops	18
Figure 3.4 Weight Matrix transferred from Fault effects in flip-flops	18
Figure 3.5 The result of same test pattern with two kinds of mask	19
Figure 3.6 A matrix sample	21
Figure 3.7 Matrix of changes when calculating mask code	24
Figure 3.8 A result of added value G after mask calculation, gray part are behalf of to be masked	27
Figure 3.9 Modification of row-column XML architecture	28
Figure 3.10 Each fault list of changes after fault simulation in every pattern	29
Figure 3.11 Flow diagram	30

LIST OF TABLES

Table 2.1 MISR states in every clock cycle	14
Table 2.2 X-masking Input-output relationship	15
Table 4.1 Exhaustive algorithm in row-column XML architecture	32
Table 4.2 Greedy algorithm in row-column XML architecture	32
Table 4.3 Expectation algorithm in row-column XML architecture	34
Table 4.4 Exhaustive algorithm with focus specific fault control pattern	34
Table 4.5 Expectation algorithm with focus specific fault control pattern	34

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