隨著通訊與多媒體儲存媒介的快速發展，人們對於視訊壓縮的需求日益增加，在要求品質的同時，還希望能夠兼顧跨平台與高壓縮率的特性，因此發展一種高效率之可調性視訊編碼標準(Scalable Video Coding, SVC)變的極為重要。
此種可調性編碼器必須符合下列需求：SNR / Temporal / Spatial / Complexity / Region-of-interest / Object-based以及Combined scalability、Error resilience及graceful degradation、base-layer 相容性、低傳輸延遲、隨機存取功能、良好的編碼效率、Supposed interlaced video等等，而由微軟亞洲研究院(Microsoft Research Asia, MSRA)所提出的Barbell-lifting Wavelet-based SVC 即為具有此一特性的視訊編碼技術。新的編碼技術運算複雜度非常高，幾乎無法以純軟體方式達成及時處理的目的，因此本論文研究透過設計硬體專屬硬體晶片的方式來提升運算速度。
在可調性視訊編碼當中影響運算複雜度最多的分別是動態預測(Motion Estimation)與熵編碼(Entropy Coding)，前者可以透過各種不同的演算法來降低複雜度，後者我們提出了一個專屬的硬體以期能提升整體之運算速度。可調性視訊編碼所使用的熵編碼Embedded Sub-band Coding with Optimized Truncation (ESCOT)中，需要較大的記憶體空間，因為每一個編碼方塊(Block)需要經過三次編碼所以較浪費運算時間，故造成不必要的功率消耗。本論文提出一個高效能的ESCOT硬體架構，以平行處理技術將編碼次數從三次降為一次提高了運算效能，同時能夠減少演算法的記憶體需求量達40%，並藉由增加少量硬體達到加快運算速度的目的與傳統架構相比此架構不但速度更快同時成本為低廉。

As the urgent demand of video sequence in multimedia applications, the video sequence compression technique becomes more and more important. It does not only require high video quality and compression efficiency, but also needs more new functions to develop more applications. Scalable Video Coding (SVC) is a novel and high efficiency coding technique and is expected as the next video sequence compression standard. It has better compression efficiency, superior video quality, error resilience, and enhanced functions than MPEG-2 and MPEG-4. The aim of SVC is to develop wide multimedia access services such that users can get multimedia information through variable devices from different locations and different platforms.
Microsoft Research Asia (MSRA) proposed the Barbell-lifting wavelet based SVC that is used the 3D wavelet transom decomposition the video sequence into different sub-bands and each sub-band is independently coded with entropy coding to be compressed. SVC is the high complexity technological and it is unable to purpose real time by software. So we must design the exclusive hardware to improve the speed of operation.
This thesis proposes a new Block Coding for ESCOT called Word-Level Process Block Coding. The Word-Level Block Coding completed two part Word-Level Process Pass Concurrent Context Modeling (Word-Level Process PCCM) and Custom Arithmetic Encoder (Custom-AE) that increase the coding efficiency and throughput of ESCOT. The Word-Level Block Coding merges the 3-pass coding to a single pass coding. In order to reduce the requirement of the internal memory for Context Modeling and the Word-Level Block Coding works in word-level operation that parallel encode multilayer bit-plans can be reduced more than 80%. Besides, the Word-Level Block Coding encodes 8 samples from 4 different bit-planes concurrently to increase the context modeling operation speed further that can support for 1080p with 60fps at clock rate of 125MHz. The proposed architecture of word-level Block Coding can increase both the operation efficiency and hardware cost significantly.

目錄
中文摘要	I
英文摘要	II
內文目錄	IV
圖表目錄	VIII

第一章 序論	1
1.1研究動機與目標	1
1.2 DWT-Base Scalable video coding簡介	3
1.2.1 編碼流程 (Coding Flow)	3
1.2.2 三維小波轉換 (3D-DWT Transform)	4
1.2.3 ESCOT熵編碼	5
1.3 本文內容	6

第二章 ESCOT演算法	7
2.1 Context Modeling	8
2.1.1 掃描順序 (Scan Order)	11
2.1.2 重要性狀態變數 (Significance State Variables)	11
2.1.3 三種編碼運算( Coding Operations )	12
2.1.4 次位元平面編碼法 ( Fractional Bit-Plane Coding )	17
2.1.5 記憶體需求 (Memory Requirement)	19
2.2 可適性算數編碼器 (Adaptive Arithmetic Encoder)	21
2.3 Rate-Distortion Optimization (R-D Optimization)	22
2.4 相關研究	22
2.4.1 Pass Parallel Context Modeling (PPCM)	23
2.4.2 Concurrent Bit-plane Context Modeling (CBCM)	23
2.4.3 平行架構 (Parallel Architecture)	24

第三章 高效能WORD PROCESS BLOCK CODING	25
3.1 Pass Concurrent Context Modeling (PCCM)	25
3.1.1 Coding Pass Merging Scheme (CPMS)	27
3.1.2 Prediction Significant Scheme (PSS)	31
3.1.3 Concurrently Encoding Architecture Scheme (CEAS)	32
3.2 Word-Level Process PCCM	33
3.2.1 Word-Level Process Scheme (WLPS)	34
3.2.2 Dual Concurrently Encoding Architecture Scheme	36
3.3 Custom Arithmetic Encoder (Custom-AE)	38

第四章 硬體架構設計	40
4.1 整體電路架構	40
4.2 Word-Level Process PCCM模組架構設計	41
4.2.1 Shift Context Box	42
4.2.2 壓縮重要性狀態變數	43
4.3 Custom AE 模組架構設計	44
4.3.1 倍頻操作	44
4.3.2 Probability Memory Bank	45

第五章 實驗結果	47
5.1 電路模擬與驗證	47
5.2 效能分析	48
5.2.1 PCCM效能分析	48
5.2.2 Word-Level Process PCCM效能分析	49
5.2.3 Word-Level Process Block Coding效能分析	50
5.2.4 工作頻率	53
5.2.5 結果歸納	56

第六章 結論	58

參考文獻 (REFERENCES)	59
附錄一 英文縮寫對照	62

圖表目錄

圖1.1 可調性視訊編碼系統簡圖	3
圖1.2 三維小波轉換	4
圖1.3 ESCOT演算法方塊圖	5
圖2.1 CONTEXT MODELING輸出入方塊圖	8
圖2.2 CODE LOCK分解示意圖	10
圖2.3 位元平面掃描順序	10
圖2.4 係數重要性狀態示意圖	12
圖2.5 ZC編碼參考之SAMPLE	13
圖2.6 SC編碼參考之SAMPLE	15
圖2.7 CODING PASS編碼步驟	17
圖2.8 獨立EMBEDDED BIT-STREAM	18
圖2.9 ARITHMETIC ENCODER輸出入方塊圖	21
圖2.10 資料階層	22
圖3.1 編碼掃描判定流程圖	28
圖3.2 編碼SAMPLE周圍狀態示意圖	30
圖3.3 狀態變數關聯圖	31
圖3.4 SAMPLE編碼重覆讀取資料示意圖	33
圖3.5 WORD-LEVEL的運算方式與BIT-LEVEL的運算方式比較	35
圖3.6 DUAL-CEAS與CEAS輸出CONTEXT分佈影響	37
圖4.1 高效能WORD PROCESS ESCOT系統架構圖	40
圖4.2 WORD-LEVEL PROCESS PCCM模組細部架構	41
圖4.3 單張FRAME的CONTEXT BOX	42
圖4.4 壓縮SIGNIFICANT STATE	43
圖4.5 CUSTOM AE模組細部架構	44
圖4.6 PROBABILITY MEMORY BANK	45
圖5.1 AKIYO的CODE-BLOCK的位元平面層數分布圖	54
圖5.2 FOREMAN的CODE-BLOCK的位元平面層數分布圖	54
圖5.3 CONTAINER的CODE-BLOCK的位元平面層數分布圖	55
圖5.4 CARPHONE的CODE-BLOCK的位元平面層數分布圖	55

表2.1 ZC編碼CONTEXT對照表	14
表2.2 SC編碼CONTEXT對照表	16
表2.3 CONTEXT MODELING 記憶體需求	20
表3.1 CODING PASS判定條件	27
表3.2 CODING PASS中SAMPLE的重要性狀態選擇表	30
表5.1 PCCM所需記憶體與面積比較	48
表5.2 PCCM編碼時間比較表	49
表5.3 WORD-LEVEL PROCESS PCCM所需記憶體與面積比較	50
表5.4 WORD-LEVEL PROCESS PCCM編碼時間比較表	50
表5.5 WORD-LEVEL PROCESS BLOCK CODING面積	51
表5.6 BLOCK CODING 所需記憶體與面積比較	51

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