本論文主要是研究在嵌入式系統中，所需的IP來源來作介紹。所謂嵌入式系統是由SOC所組成。單晶片系統(SoC)為許多應用提供整合的解決方法，例如電腦系統、通訊、多媒體與消費性電子產品等。在設計單晶片系統時最主要挑戰之一是如何使工作在不同頻率、具有不同特性的異質元件間能相互通訊。而SOC是將一些所需的功能如CPU、RAM或LAN功能整合在一個晶片上。我們的研究目的是作出一網路系統晶片，此晶片具有簡單的封包辨識功能。而取得IP的主流方法是購買已授權的IP。如從ARM取得CPU的IP，從TI取得LAN的IP等等。而在這種方法下，雖然可以快速而正確的作出晶片模擬，但所需的費用卻是相當的高。在此篇論文中，我們採用了一個FREE-WEBSITE (WWW.OPENCORE.ORG)來作為IP的來源。在此網站中，我們可以取得一些FREE的IP來作應用。
我們下載了一個網路MAC來做研究與分析，其中包含了控制層的傳送與接收的功能性驗證以及一些效能上的統計等等。在控制層的傳送與接收的功能性驗證方面，我們選擇以ModelSim SE這個軟體來做編譯及模擬，從這個軟體的模擬的時序圖來分析。

關鍵字:嵌入式系統，矽智財。

This thesis is mainly studied in the embedded system, necessary IP source comes to do an introduction. The so-called embedded system consists of SOC. System-on-chip (SoC) designs provide integrated solutions to many applications such as computer systems, multimedia, consumer electronics, etc. One of the major challenges of designing a SoC chip is the communication architecture between heterogeneous components running different frequencies and possessing different characteristics. And SOC combines some necessary functions on a chip such as CPU, RAM or LAN function. Our research purpose is to make a chip of one network system having a function to distinguish packages .The major method to get IP is to buy authorized IP. For instance, we can obtain IP of CPU from ARM, or obtain IP of LAN from TI, etc. Under this kind of method, though we can make chip simulation fast and correctly, the necessary expenses are quite high. In this page thesis, the source as IP that we have adopted is from one FREE-WEBSITE (WWW.OPENCORE.ORG ). In this website, we can obtain some FREE IP to do the application, and integrate these FREE IP to a network system chip. 
   We use a popular language- VERILOG to build these codes. After MODELSIM compile these codes, we can simulate those waveform to make sure its function is OK.

論文提要..................................................Ⅰ
英文提要..................................................Ⅲ
誌謝......................................................Ⅴ
圖目錄................................................... Ⅸ
表目錄....................................................XI
CHAPTER 1 導論.............................................1
1.1研究動機與目的..........................................1
1.2論文組織................................................4
CHAPTER 2 相關研究整理.....................................5
2.1 嵌入式系統概說.........................................5
2.2 嵌入式系統微處理器.....................................9
2.3 硬體描述語言(HDL)介紹.................................11
2.3.1 硬體描述語言(HDL) ..................................11
2.3.2 Verilog HDL.........................................14
2.3.3 Verilog 與VHDL 的比較...............................18
2.4 IP及License介紹.......................................20
2.5 Opencore 介紹	........................................20
2.5.1 WISHBONE Interface..................................22
CHAPTER 3晶片網路的研究介紹...............................28
3.1晶片網路介紹...........................................28
3.2 OPENCORE 網路MAC介紹..................................31
3.2.1 TXMAC的介紹.........................................33
3.2.2 RXMAC的介紹.........................................35
CHAPTER 4 網路晶片實作與測試..............................37
4.1 OPENCORE Ethernet Code的檔案架構......................37
4.1.1 Ethernet Code的檔案架構.............................37
4.1.2 Ethernet Code modules的介紹.........................38
4.2 模擬..................................................41
4.3 Summary...............................................42
4.3.1 建立測試環境........................................42
4.3.2 存取控制層傳送功能驗證..............................43
4.3.2.1 傳送64bytes封包...................................43
4.3.2.2 傳送128bytes封包..................................46
4.3.3 存取控制層接收功能驗證..............................49
4.4 RTL Code LeveL（Synthesis to gate level）.............52
Chapter 5 結論與未來研究..................................54
5.1 結論..................................................54
5.2 未來研究..............................................55
參考文獻..................................................56
圖目錄
圖 2.1 新興的嵌入式系統產品................................6
圖2.2 嵌入式產業之技術需求與用戶需求.......................9
圖2.3 兩個模組之間的連線關係與程式寫法....................15
圖2.4 測試平台與功能模組間的關係..........................17
圖2.5 Opencore的IP列表....................................21
圖2.6 WISHBONE 連接IP 模組的方式..........................23
圖2.7 WISHBONE Interface Controller Block Diagram...........25
圖3.1 晶片網路的協定堆疊..................................29
圖3.2 TX MAC 的方塊示意圖..................................34
圖3.3 RXMAC 的方塊示意圖..................................36
圖4.1 Ethernet Code modules的示意圖........................39
圖4.2 Modelsim的Simulator.................................42
圖4.3 建立測試環境........................................43
圖4.4 開始送出Preamble....................................44
圖4.5 送出Preamble 與SFD(以16 進位值表示) ................44
圖4.6 送出frame(60bytes)內容(以16 進位值表示) ............45
圖4.7 送出frame 內容及CRC 碼(以16 進位值表示) ............46
圖4.8 開始送出Preamble....................................47
圖4.9 送出Preamble 與SFD(以16 進位值表示) ................47
圖4.10 送出frame(124bytes)內容(以16 進位值表示) ..........48
圖4.11 送出frame 內容及CRC 碼(以16 進位值表示) ...........49
圖4.12 RXMAC在MRxD上收到Preamble 與SFD...................50
圖4.13 RXMAC在MRxD上收到目標位址(以16進位表示) ..........50
圖4.14 開始將資料區塊送上匯流排(以16 進位表示) ...........51
圖4.15 訊框內容全部放上匯流排(以16 進位表示) .............52
表目錄
表2.1各種不同等級的嵌入式系統微處理器應用.................10
表2.2 Verilog HDL 邏輯準位.................................16
表2.3 VHDL 與Verilog HDL 比較表...........................19
表2.4 WISHBONE Host Interface Ports.........................26
表3.1 PHY Interface 的訊號列表.............................32
表3.2 TX DATA、TX Control signals列表.....................34
表3.3 RX DATA、RX Control signals列表......................36
表4.1 Cadence ETHERNET NETWORKING..........................53

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