在現今的SOC架構設計中，邏輯閘數目越來越多，伴隨著來的是大量的測試資料產生。如果要測試如此大的電路，由於測試通道容量的不足和自動測試機台(Automatic Test Equipment, ATE)的記憶體限制，且量大的時候將很耗時和耗電，因此測試資料的壓縮工作就變得更為重要。
我們利用MISR(多重輸入位移暫存器)的相關特性，可使用一個自動測試機台的資料跑很多次，在架構中我們使用數個正反器組成選擇器來擴散傳遞多重輸入位移暫存器的資料，每個多重輸入位移暫存器的正反器連接著兩個選擇器的多工器，選擇器則連接著多重輸入位移暫存器。利用正反器儲存位元組在裡面，若要改變測試資料，只要改變正反器的位元組即個。正反器中的位元組並不會很頻繁的改變，所以我們就可以降低功率消耗。
在我們的架構中我們已經解決了部分的位移功率，在此之上我們使用一個低擷取功率的X-filling 方法來降低正反器位移次數。跟一般的隨機X-filling方法比較，我們可以得到一樣的錯誤涵蓋率但是更少的平均和最大轉換次數。

In the system-on-chip (SOC) design, there are a huge volume of test data. The arrival of test data compression is because of lacking in channel capacity and the restricted memory of Automatic Test Equipment (ATE). Therefore, the technique of test data compression is very important to save time and memory.
Because of MISR’s characteristic, we can use one ATE data to run many times. In this paper, we use selection with Flip-Flops to spread MISR data. Each Flip-Flop of MISR is connecting with 2 MUXs of selection. In addition, selection connected with MISR. To use Flip-Flops so we can restore bits in it, just changing Flip-Flops bits when data changing. It is not frequently changing of the bits of Flip-Flops, so we can decrease power consumption.
In our architecture, we already saved sift power. In this paper, we will approach a Low-Capture-Power X-Filling Method to decrease shift times of Flip-Flops. Compare to Random X-filling Method, the Fault Coverage will be the same but less average and maximum shift times.

中文摘要	II
英文摘要	III
TABLE OF CONTENT	IV 
LIST OF FIGURES	VI
LIST OF TABLES	VII
CHAPTER1. INTRODUCTION	1
1.1 MOTIVATION	1
1.2 ISSUE OVERVIEW	2
1.3 THESIS OVERVIEW	3
CHAPTER2. KNOWLEDGE USED IN PAPER	5
2.1 DETECT A FAULT	5
2.2 FAULT SIMULATION	9
2.3 SCAN-CHAIN DESIGN	11
2.4 CAPTURE POWER	14
2.5 SHIFT POWER	15
2.6 LINEAR FEEDBACK SHIFT REGISTER (LFSR)	17
CHAPTER3. OVERVIEW OF ARCHITECTURE	19
CHAPTER4. PROPOSED METHOD	21
4.1 OVERVIEW	21
4.2 X-FILLING ALGORITHM	24
4.3 TYPR-R	24
4.4 TYPE-C	25
4.5 TYPE-D	25
4.6 TYPE-E	26
CHAPTER5. EXPERIMENT RESULTS	28
CHAPTER6. CONCLUSIONS	30
REFERENCES	31

 
List of figures
Figure 2.1 Example of OR gate faults…………...…………………………….6
Figure 2.2 Example of AND gate faults…………………………...…………..7
Figure 2.3 Fault Coverage (FC)……………………………………………….8
Figure 2.4 Parallel Fault Simulation…………………………………………10
Figure 2.5 Example of regular Scan-chain circuit…………………….…...…11
Figure 2.6 (a) A Muxed-D Scan Element (b) A Sample of Scan-Chain……..12
Figure 2.7 Common Scan-Chain Circuit……………………………………..14
Figure 2.8 Example of Capture Power Program……………………………...15
Figure 2.9 Example of Shift Power Program…………………………………17
Figure 2.10 LFSR (Linear Feedback Shift Register) Types………………….18
Figure 3.1 Overview of Architecture…………………………………………20
Figure 4.1 Proposed X-filling method Flow………………………………….23

List of Tables
Table 4.1 Types of X-filling methods of PPI and PPO…………………..….22
Table 5.1 Results of Proposed X-filling Method…………………………….29
Table 5.2 Comparison Our Results with Other Method……………………...29

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