近年來對於可攜式電子裝置需求日益增高，相關產品如雨後春筍般被上市，此類產品由於講究可以隨身攜帶，因此對於省電要求也相對提高。為了因應此需求，低電壓低功率產品已經陸續被開發出來。低電壓低功率已經為現在之趨勢，預估未來2010年時，CMOS電路供應電壓可下降至0.7V[32]。隨著製成的推進電壓之下降可以達到更高頻率以及更低之消耗功率。雖然電壓之下降對數位電路有上述之優勢，但是類比電路會比預期來的難以設計，要維持與高電壓相匹配之性能，勢必為一大挑戰。

 在現今晶片應用當中，類比數位轉換器為一系統之重要部份。其目標為到達高解析度以及低功率，其常見實現的架構眾多，包括快閃式數位類比轉換器(Flash A/D)、管線式類比數位轉換器(Pipeline A/D)、三角積分調變器(Delta sigma modulator)等。其中各有其優劣，然而要到應用於高解析度(16-bit)音頻(Audio)應用的話，三角積分調變器是非常適合去完成的。由於它對無論是運算放大器之增益或電路之間的誤差相對較不敏感，這些特性應用於低電壓電路十分合適，因此本論文使用三角積分調變器來達成低電壓之設計。
    本論文提出兩種架構之低電壓調變器，第一種是建立於低雜訊架構之多級串疊架構，此架構有較低之輸出擺幅以及較大之動態範圍(DR)，非常適合在低電下下操作。每級分別提供二階雜訊移頻，總共可提供四階雜訊移頻而沒有穩定度問題。模擬結果最大的訊號雜訊比可達到89dB，在1V的供應電壓下，消耗功率只有900微瓦，取樣頻率為4MHz。另一架構為低電壓多位元調變器，本論文提出新架構之數位類比轉換(DAC)回授，用來克服開關浮接的問題，在1V的供應電壓下，消耗功率為1.8毫瓦，時脈頻率為2.5MHz，量測結果最大訊號雜訊比為80dB。

The trend towards low voltage, low power, portable audio products has been growing quickly. There is a deep desire to develop low power and low voltage circuitries. Today the 90nm generation uses 1.2V supply voltage and it will be scaled down to under 0.7V for 2010[32]. The supply voltage will be decreased when CMOS process scales down, and furthermore it could be achieved low power, low cost and high speed systems. 
There are some structures to implement ADCs, such as pipeline ADC, flash ADC, etc. In high resolution application, the switched-capacitor (SC) technique is the most popular approach for implementing ADCs due to the precise ratio on the integrated capacitors. Especially the delta sigma modulator is suitable to realize a high resolution application. Due to delta sigma modulators are insensitive on analog components such as opamp and comparator. The requirement of oversampling converter can be relaxed. It not only achieves high resolution more easily but also reduces the power dissipation. However, the supply voltage is descending with the scaling technologies. It is a great challenge to design a desired performance when the supply voltage is reduced.
The aim of this thesis is to design a low-power and low-voltage delta sigma modulator. There are two works in this thesis. First, a 1V 2-2 MASH delta sigma modulator is based on low distortion structure. The simulated total power dissipation is only 0.9mW. The peak SNDR of the modulator is 89dB within a bandwidth of 22.05kHz. Second, a 1V multibit delta sigma modulator using a single-opamp is proposed. The peak SNDR of the second-order modulator is 82dB within a bandwidth of 22.05kHz. The measured total power dissipation is 1.8mW.

CHAPTER 1	1
INTRODUCTION	1
1.1 Motivation	1
1.2 Organization	2
CHAPTER 2	3
FUNDAMENTALS OF delta-sigma MODULATOR	3
2.1 Introduction	3
2.2 Performance Metrics	4
2.3 Quantization Noise	5
2.4 Oversampling	7
2.5 First-Order Noise Shaping	9
2.6 Second-order Noise Shaping	11
2.7 Higher-order noise shaping	12
2.8 Cascaded Topologies	14
CHAPTER 3	18
THE DESIGN OF LOW VOLTAGE SWITCHED-CAPACITOR CIRCUITS FOR delta-sigma MODULATORS	18
3.1 Introduction	18
3.2 Low Voltage Switched-Capacitor Circuits	18
3.2.1 Low-threshold Voltage Process	20
3.2.2 Voltage Boosting Technique	20
3.2.3 Bootstrapped Switch	21
3.3 The Switched Opamp Principle	22
3.3.1 Fully Differential Switched Opamp	24
3.3.2 Common Mode Feedback (CMFB)	25
3.3.3 Sampling Capacitor	25
3.3.4 Finite Gain of the Amplifier	26
3.3.5 Finite Amplifier Bandwidth and Slew-Rate	27
3.3.6 Non-ideal MOS Switch	28
3.3.7 Charge Injection and Clock Feedthrough	30
3.3.8 Simulation Results	30
3.4 Low Voltage Quantizer	33
CHAPTER 4	35
A 4TH ORDER 2-2 CASCADE DELTA-SIGMA MODULATOR	35
4.1 Introduction	35
4.2 System Consideration	35
4.3 Cascade Delta Sigma Modulator	37
4.4 Circuit Implementation	40
4.5 Simulation Results	44
CHAPTER 5	48
A DOUBLE-SAMPLING 2ND-ORDER MULTIBIT DELAT-SIGMA MODULATOR USING A SINGLE SWITCHED-OPAMP	48
5.1 Introduction	48
5.2 System Considerations	48
5.3 Implementation of the Circuit	50
5.3.1 The Multiplexers	56
5.3.2 Flash A/D	57
5.4 Dynamic Element Matching	59
5.4.1 DWA	59
5.4.2 Tree Structure	60
5.5 The Clock Generator	61
5.6 Experimental Results	64
5.6.1 Input Signal Source and Input Termination Circuit	65
5.6.2 Power Supply and Ground	65
CHAPTER 6	70
CONLUSIONS	70
6.1 Conclusions	70
6.2 Future Works	70
BIBLIOGRAPHY	71


List of Figures

Figure 2.1 Block diagram of a Nyquist-rate ADC	3
Figure 2.2 Block diagram of an oversampling ADC	3
Figure 2.3 SNDR versus signal power of an ADC	5
Figure 2.4 Quantizer transfer and quantization error (a) N-bit (b) One-bit	6
Figure 2.5 (a) Probability density function of the quantization error (b) Power spectral density of quantization	6
Figure 2.6 Quantization noise power spectral density	8
Figure 2.7 (a) The architecture (b) First-order ΔΣ modulator	9
Figure 2.8 (a) Noise transfer function (b) The power spectral density of first order delta-sigma modulator	10
Figure 2.9 Second-order ΔΣ modulator	11
Figure 2.10 The power spectral density of the first-order and the second-order noise-shaping	12
Figure 2.11 SNR improvements for higher-order modulators	13
Figure 2.12 Linear model of modulator	14
Figure 2.13 Root locus of (a) Second order modulator (b) Third order modulator	14
Figure 2.14 Block diagram of cascaded topology	15
Figure 2.15 (a) 3-bit quantizer (b) 4-bit quantizer	17
Figure 3.1 (a) Switch conductance with VDD=1.8V (b) Switch conductance with VDD=1V	19
Figure 3.2 Conventional switched capacitor integrator	19
Figure 3.3 Clock boosting circuit	20
Figure 3.4 Clock bootstrapped switch	21
Figure 3.5 Implementation of bootstrapped switch	21
Figure 3.6 A full delay integrator with extra switched opamp	22
Figure 3.7 A half delay integrator without extra switched opamp	22
Figure 3.8 (a) The modified switched opamp integrator (b) The input stage DC level of the switched opamp	23
Figure 3.9 Schematic of switched-opamp	24
Figure 3.10 The bias circuit	24
Figure 3.11 (a) Dynamic common mode feedback (b) The schematic of the CMFB OTA	25
Figure 3.12 (a) Sampling phase (b) Integration phase	26
Figure 3.13 Step response	28
Figure 3.14 Non-zero on resistance of the switches	29
Figure 3.15 Charge injection and clock feedthrough (a) NMOS on (b) NMOS off (c) NMOS overlap capacitances	30
Figure 3.16 AC response of the switched-opamp	31
Figure 3.17 Output swing of switched-opamp	31
Figure 3.18 Gain nonlinearity of switched opamp	32
Figure 3.19 The transient response of switched opamp output	32
Figure 3.20 Schematic of low voltage comparator and SR-latch	33
Figure 3.21 (a) Hysteresis (b) Transient response	34
Figure 3.22 Schematic of low voltage comparator and SR-latch	34
Figure 4.1 (a) Traditional topology (b) Low distortion topology	35
Figure 4.2 Comparison between traditional and low distortion topologies	36
Figure 4.3 Each outputs swing of integrator (a) Traditional topology (b) Low distortion topology	37
Figure 4.4 Block diagram of 2-2 cascaded delta sigma modulator	38
Figure 4.5 Digital noise cancellation logic	38
Figure 4.6 SNDR V.S the opamp DC gain	38
Figure 4.7 Output swings of integrators	39
Figure 4.8 (a) Peak SNDR of system level simulation (with KT/C) (b) DR of system level simulation	39
Figure 4.9 First stage	42
Figure 4.10 Second stage	43
Figure 4.11 Clock generator	44
Figure 4.12 Simulated clock signals	44
Figure 4.13 Input waveform of switched-opamp	45
Figure 4.14 The simulation results of integrator outputs	45
Figure 4.15 (a) The output power spectrum (b) SNDR V.S supply voltage	46
Figure 4.16 IC layout	46
Figure 4.17 (a) Pin configuration diagram (b) Pin assignments of the chip	47
Figure 5.1 The block diagram of second order delta-sigma modulator	49
Figure 5.2 A single-loop second-order delta-sigma modulator with a single SOP	50
Figure 5.3 Four states: (a) s1, (b) s2, (c) s3, and (d) s4 of the integrator	51
Figure 5.4 The corresponding clocks	51
Figure 5.5 (a) A conventional 9-level DAC feedback (b) A new 9-level delay-free DAC feedback (c) A new 9-level half-delay DAC feedback.	52
Figure 5.6 The multibit DAC by multiplexer	57
Figure 5.7 (a) The 9-level quantizer with differential comparator (b) The 9-level quantizer with differential difference comparator	58
Figure 5.8 Power spectral density	59
Figure 5.9 Operation of the DWA	60
Figure 5.10 (a) Tree structure (b) Operation principle	60
Figure 5.11 (a) Implementation of tree structure (b) Switching block	61
Figure 5.12 The clock generator	62
Figure 5.13 The simulation results of the clock generator	62
Figure 5.14 The second order integrator	63
Figure 5.15 Experimental test setup	64
Figure 5.16 Photographs of (a) Audio Precision (b) Logic analyzer TLA5201	64
Figure 5.17 Input termination circuit	65
Figure 5.18 The regulator circuit	66
Figure 5.19 (a) The reference voltage circuit (b) The filter tank for the supply voltage	66
Figure 5.20 The photograph of the experimental DUT board	66
Figure 5.21 (a) Pin configuration diagram (b) Pin assignments of the chip	67
Figure 5.22 (a) The Die photograph (b) The digital outputs	68
Figure 5.23 (a) Measured output power sptctrum (b) SNDR V.S input power	68

List of Tables

Table 3.1 Performance summary of simulation results of switched opamp	33
Table 4.1 Performance summary of the 2-2 MASH	47
Table 5.1 The corresponding table of active code for delay free	53
Table 5.2 The corresponding table of active code for half delay	55
Table 5.3 The corresponding table of active code for half delay	55
Table 5.4 The corresponding table of exchanged thermoneter code	56
Table 5.3 The performance of the delta-sigma modulator	69

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