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系統識別號 U0002-0706201114262000
中文論文名稱 最佳化演算法應用於時脈繞線之實現
英文論文名稱 Optimization Algorithm Applied to Zero Skew Clock Tree Implementation
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 99
學期 2
出版年 100
研究生中文姓名 林志忠
研究生英文姓名 Chih-Chung Lin
學號 698440053
學位類別 碩士
語文別 中文
口試日期 2011-05-26
論文頁數 39頁
口試委員 指導教授-李揚漢
委員-周允仕
委員-曾憲威
委員-錢威
委員-詹益光
中文關鍵字 時脈樹  零時脈傾斜  時脈延遲  粒子群最佳化演算法 
英文關鍵字 Clock Tree  Zero Clock Skew  Clock Delay  Particle Swarm Optimization 
學科別分類 學科別應用科學電機及電子
中文摘要 本論文,在系統晶片中我們提出了一個採用了1) FED(Fitted Elmore Delay) 延遲模型所導出的非直線型的分接點,結合2)利用粒子群最佳化(Particle Swarm Optimization, PSO)演算法的優化特性,將時脈繞線的連線形狀由類H型變成類X型,找出四點的最佳分接點,達到在零時脈傾斜(Zero Clock Skew)下,有效的減少時脈繞線的總線段長和時脈延遲(Clock Delay)的目的。
我們提出「最佳化演算法應用於時脈繞線之實現」的方法,實驗證明顯示此方法,跟傳統λ-Geometry DME routing方法比較,在同樣的測試例子下,及在達到零時脈傾斜(Zero Clock Skew)下,有效的減少時脈繞線的總線段長19%~5%和時脈延遲(Clock Delay) 14%~-22%。證明了將H形狀轉成X形狀是可行的並且有效。

關鍵詞 : 時脈樹、零時脈傾斜、時脈延遲、粒子群最佳化演算法
英文摘要 In this paper in the system on chip design, we propose a method to determine a nonlinear branch connection location in the timing pulse wiring design that is 1) based on Fitted Elmore Delay model and it then combines 2) the evolution characteristics of the Particle Swarm Optimization (PSO) algorithm to change the connection topology of timing pulse wiring from H shape to X shape; it determine and finds, under the requirement of Zero Clock Skew, the best branch location in the X shape wiring. With this design it can effectively reduce the total required wire length of the timing pulse wiring and reduce the overall timing pulse delay.
We propose the methodology of ‘Optimization Algorithm Applied to Zero Skew Clock Tree Implementation’ and from many test experiments under the requirement of Zero Clock Skew it reveals that our proposed design algorithm, comparing with the conventional λ-Geometry DME routing method, can effectively reduce the total wiring length of the timing pulse wiring by 5% ~ 19% and clock delay by 14%~-22% ; consequently it appears that our proposed algorithm by changing the conventional H shape into X shape in the wiring design is a realizable and effective design methodology.
論文目次 目錄
第一章 緒論 ..............................................1
1.1 研究動機與目的 ..........................................1
1.2 回顧時脈繞線相關背景知識...................................4
1.2.1 時脈設計方法...................................4
1.2.2 各種時脈繞線法.................................5
1.3 論文章節內容簡述..........................................7
第二章 延遲模型............................................9
2.1 導論...................................................9
2.2 FED延遲模型.............................................9
2.2.1 直線型的分接點........................................10
2.2.2 非直線型的分接點.......................................12
第三章 時脈繞線法.........................................15
3.1 叢集方式...........................................15
3.1.1導論.........................................15
3.1.2 MMM(Method of means and Medians)...........15
3.2 最佳化演算法應用於時脈繞線................................17
3.2.1導論.........................................17
3.2.2 PSO應用於時脈繞線之實現........................19
第四章 實驗結果...........................................22
4.1模擬參數及測試例子設定....................................22
4.2模擬與效能分析...........................................24
第五章 結論與未來展望......................................33
參考文獻..................................................36

圖目錄
圖1.1 典型的SoC結構圖與系統時脈的關係...........................2
圖1.2 SoC的時脈延遲.........................................2
圖1.3 SoC的時脈傾斜.........................................3
圖1.4 時脈週期的等效邏輯圖....................................4
圖1.5 實驗流程圖............................................8
圖2.1 以FED延遲模型表示的單一導線線段..........................10
圖2.2 以FED延遲模型表示合併兩個子樹............................11
圖2.3 FED模型加入Snaking的意示圖.............................12
圖2.4 直線型的分接點與非直線型的分接點的示意圖...................12
圖2.5 四點對角線的交點.......................................14
圖2.6 四點X型與H型的繞線的示意圖..............................14
圖3.1 MMM procedure code..................................16
圖3.2 MMM分群法實例.........................................17
圖3.3 H形狀與X形狀的示意圖...................................18
圖3.4 PSO應用於時脈繞線之實現流程圖...........................21
圖4.1 測試例子8點(MMM+DME).................................25
圖4.2 測試例子8點(Optimization Algorithm)..................26
圖4.3 測試例子16點(MMM+DME)................................27
圖4.4 測試例子16點(Optimization Algorithm).................28
圖4.5 測試例子32點(MMM+DME)................................29
圖4.6 測試例子32點(Optimization Algorithm).................30
圖4.7 測試例子64點(MMM+DME)................................31
圖4.8 測試例子64點(Optimization Algorithm).................32
圖5.1 對稱分群後示意圖......................................34
圖5.2 不對稱分群示意圖......................................34

表目錄
表4.1 Fitted Elmore Delay(FED)延遲模型模擬參數設定............22
表4.2粒子群最佳化演算法模擬參數設定.............................23
表4.3 測試例子模擬參數設定....................................23
表4.4 連線長度比較..........................................24
表4.5 延遲時間比較..........................................24

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