在現今的IC測試領域中，因為電路設計的複雜度越來越高，使得測試資料與日俱增，而在測試資料當中，未知向量又會占去大部分的測試容量及空間，不但浪費時間，佔去測試時的資料空間，更進一步影響資料壓縮率，造成測試者的負擔。
     本文章內容，是利用叢集式壓縮法，在未知向量上，加上X填入法，使得整個壓縮率得以提升，解決一般測試者對未知向量的困擾，我們將叢集式壓縮法先做Group的分類，再以Cluster Number =2的情況下，對未知向量做固定值的填入(遮罩)，如此得以改善壓縮率，也因未知向量視為固定值，減少了壓縮資料失真的問題。

One of IC tester’s problems is the larger and larger test data volume due to the complexity of the circuit design. Furthermore, since the unknown generated during the test procedure is taking a major part of the test data volume and space, it has become a waste of time and a burden, affecting rate of data compact.

     In this study, we combine clustering-approach with filling in X to substitute the unknown. By doing so, we solve the problem of the unknown and thus upgrade the compression rate. Take our case as an example, we first classify the clusters into groups and fill in a fixed number when cluster number equals 2. The outcome is a higher compression rate and no loss of data.

中文摘要..................................I
英文摘要..................................II
第一章	緒論…………………………………………1

1.1	簡介…………………………………………...1
1.2	研究動機與目的……………………………...1
1.3	章節介紹……………………………………...3

第二章	叢集式壓縮法簡介與原理………………….4

2.1	簡介……………………………………………4
2.2	原理……………………………………………4
2.3	壓縮法之Position分類………………………8
2.4	壓縮法之Index合併…………………………13

第三章	未知向量X填入法…………………………16

3.1	簡介……………………………………………16
3.2	原理……………………………………………16
3.3	未知位元填入法………………………………18
3.4	分解前置資料…………………………………19
3.5	解壓縮的硬體電路……………………………22

第四章	未知向量X填入法與叢集式壓縮的結合…..23

4.1	簡介……………………………………………23
4.2	原理……………………………………………23
4.3	填入未知向量固定值…………………………24
4.4	叢集式壓縮……………………………………25

第五章	測試資料實驗結果………………………….28
第六章	結論………………………………………….30
  
6.1	結論……………………………………………30
6.2	分析結果………………………………………30
6.3	未來實驗方向…………………………………31

參考文獻………………………………………………32
    

       圖目錄
Fig 1.   A simple circuit used to motivate the clustering-based approach………………………………………...6
Fig 2.   An example to illustrate the extraction of frequently occurring..............................................................6
Fig 2.2  Clustering for position grouping.……………...10
Fig 2.2.1 Clustering for position grouping………………11
Fig 2.3  Clustering for position grouping.……………...11
Fig 2.3.1 Clustering for position grouping………………11
Fig 2.3.2 Clustering for position grouping………………12
Fig 2.3.3 Clustering for position grouping………………12
Fig 2.4  Clustering for position grouping………….…...12
Fig 2.5  Clustering for position grouping………….…...14
Fig 2.6  Clustering for position grouping……………....14
Fig 2.7  Clustering for position grouping……………....15
Fig 2.8  Clustering for position grouping……………....15
Fig 3.1  Diagram of proposed scheme…………….........17
Fig 3.2  Example of proposed unspecific fix scheme…..18
Fig 3.3  Encoding Scheme……………………………...20
Fig 3.4  Encoding Scheme……………………………...21
Fig 4.1  Example of proposed encoding scheme……….25
Fig 4.2  Example of proposed clustering for position grouping…………………………………….....26
Fig 4.3  Example of proposed clustering for position grouping……………………………………….27
Fig 5.1  Test Benchmark..................................................28
Fig 5.2  Results for proposed scheme on test benchmark
        …………………………………………….......29

[1]	Lei Li and Krishnendu Chakrabarty “Hybrid BIST Based on Repeating Sequences and Cluster Analysis” in Proc. IEEE 1530-1591, 2005
	
[2]   Chih-Ping Su “A Filling Methodology for Efficient Compaction of Test Responses with Unknowns.” Electrical Engineering, Tamkang University, June, 2010。

[3]	O. Sinanoglu and S. Almukhaizim, “X-Align: Improving the Scan Cell Observability
	of Response Compactors” IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 17, no. 10, October, 2009.

[4]	A. Jas, J. Ghosh-Dastidar, M. Ng, and N. A. Touba, “An Efficient Test Vector
	Compression Scheme Using Selective Huffman Coding” in Proc. IEEE Trans.
	Comput-Aided Des., 22(6), 2003, pp. 797-806.

[5]	D. A. Huffman, “A Method for the Construction of Minimum Redundancy Codes” in
	Proc. IRE, 40(9), 1952, pp. 1098-1101.

[6]	C. V. Krishna and N.A. Touba, “3-Stage Variable Length Continuous-Flow Scan
	Vector Decompression” in Proc. IEEE VLSI Test Symp. (VTS’04), April 2004,
	pp. 79-86.

[7]	K.J. Lee, J. J Chen, and C. H. Huang, “Using a Single Input to Support Multiple
	Scan Chains” in Proc. Int. Conf. on Computer-Aided Design, November 1998,
	pp. 74-78.

[8]	I. Hamzaoglu and J. H. Patel, “Reducing Test Application Time for Full Scan
	Embedded Cores for System-On-A-Chip Test” in Proc. IEEE Trans. Comput-Aided
	Des., 22(6), 2003, pp. 783-796.
[9]  A. Chandra and K. Chakrabarty, “Test data compression and test re-source partitioning for system-on-chip using frequency-directed run-length(FDR) codes”, IEEE Trans. Computers, vol. 52, pp. 1076-1088, August 2003.

[10]  B. S. Everitt, S. Landau, and M, Leese, Cluster Analysis, Oxford University press Inc., New York, NY, 2001.

[11]  A. Jas, C. V. Krishna and N. A. Touba, “Hybrid BIST based on weighted pseudo-random testing: a new test resource partitioning scheme,” Proc. VTS, pp. 2-8, 2001.

[12]  C. V. Krishna, A Jas and N. A. Touba, “Test vector encoding using LFSR reseeding, ”Proc. ITC, pp. 885-893, 2001.

[13]  L. Li and K Chakrabarty, “Test data compression using dictionaries with fixed-length indices, “ Proc. VTS, pp. 219-224, 2003.