SoC的設計除了需要克服各方塊之間複雜的匯流排資料轉換外
，還要精準的提供每一方塊內部所需的時脈訊號與電源訊號，以確
保整個系統能正常工作。而時脈訊號的產生往往伴隨著大量的功率
消耗、雜訊的產生與大面積的被動元件需求。在一個高整合度的設
計中這些不利因素往往需要藉著電路架構的更新才能有所突破，本
文的研究便著重在一個全新的頻率合成器架構，試著解決傳統的頻
率合成電路過於複雜及功耗與面積過大的問題。
    利用一個具有可程式化輸出頻率的鎖向迴路所產生的多相位
差動時脈訊號，再輔以具分數功能的頻率除法器，便可產生SoC
設計中所需的多種時脈頻率。而本文所提出的演算方法除了可以正
確找出系統所需頻率，亦成功的達到僅利用兩個主要的鎖相迴路便
可產生x86個人電腦系統內所需的二十多個時脈訊號的目標。
    在新的頻率合成器架構中更新了兩個主要電路方塊。一個是
具有EOC Detecting and Reloading Algorithm特性的可程式除法
器，主要是簡化其detector電路並改善其reload訊號品質達到擴
展其工作頻寬與位元數擴充的目的，同時並修正了原本電路中高
頻時會發生的輸出鎖死情形。此除法器主要是用在鎖相迴路的VCO
到PFD之間的迴路中，使得VCO的高頻率輸出可被程式化。更新
後的除法器可以工作在1MHz到3.5GHz。另外，在VCO之後的後
級除法器部份，捨棄了傳統的分數除法器架構，利用相位組合的
方式，選擇VCO差動式輸出中的多個等距相位，組合出系統所需
的頻率相位來。不僅沒有傳統分數除法器中VCO頻率與所需輸出頻
率絕對相依的缺點，更具有多頻率同時輸出、輸出相位與Duty可
程式化和相位穩定等優點。
    新的頻率合成器架構針對SoC設計提供了時脈訊號優化的方
法，解決了功耗與面積過大問題，並具有可程式化的微調功能。此
頻率合成器可以是SoC設計中不可或缺的重要方塊，也可以是獨立
完整的IP元件。架構中僅使用簡易與成熟的電路方塊將其高度模
組化，這使得SoC在設計應用上增加更多的彈性與可能。

Beside to overcome the complex bus data transformation, the most challenges of SoC design still need to provide precise clock signals and power trails for each internal block to make sure the whole system can working well.
  In a multi-functions single ship design, the generating of necessary clock signals always accompanies higher power consumption, more noises, and bigger layout area for passive components. Usually, these drawbacks can only be solved by modifying block diagram and circuit structure. We focus on studying a new frequency synthesizer structure to meet the SoC design clock requirements and try to overcome the power consumption issue, area problem, and the complexity of clock tree routing in using traditional frequency synthesizer for SoC design.
  The using of multi-phases clocks that output from a phase-locked loop to be inputs of pseudo fractional-N divider can generate multi-clocks without multiple relationships. These frequency independent clocks can satisfy complex demands of SoC design. In this thesis, presented algorithm can exactly find required VCO stage number and frequency. Another target of proposed algorithm is to minimize required phase-locked loop number.
  Two major circuit blocks are modified for performance improving. The first modified block is the programmable divider with EOC Detecting and Reloading Algorithm functions. This divider is an integer divider which connects one of VCO outputs with PFD to perform a programmable phase-locked loop. The detect circuit of this divider is simplified and the latency of its reload signal is optimized for improving bandwidth. These modifications make the divider can working between 1MHz to 3.5GHz. The high frequency dead-lock issue is also fixed. 
  The second modified block is the output stage dividers that connect behind VCO. This block is called as Pseudo Fractional-N Divider. It is one of the most important sub circuits in this frequency synthesizer. This pseudo fractional-N divider uses selected VCO output phases as its inputs for combining final SoC clocks. The pseudo fractional-N divider can help to cancel the frequency dependence of VCO and final SoC clocks. With lot of other advantages, the pseudo fractional-N divider can synchronize output clocks, make output phases and duty programmable, and improve output jitters.
  This paper presents a new frequency synthesizer structure to simplify clock tree in complex SoC design. The improving of power consumption, layout area, and programming ability drives SoC design to a higher flexibility for IPs integration. The proposed frequency synthesizer can be use as an embedded sub block in SoC design or an independent discrete IP for system implementation. Only mature circuit blocks are used to composing circuit modules, thus it forces the SoC design to have more possibility.

TABLE OF CONTENTS
CHAPTER 1    INTRODUCTION	- 1 -
1.1	SOC INTRODUCTION	- 1 -
1.1.1	SoC marketing trend	- 4 -
1.1.2	SoC technology trend	- 4 -
1.1.3	SoC trend on x86-based personal computer	- 6 -
1.2	MODERN X86-BASED PC PLATFORM CLOCK SCHEME	- 8 -
1.3	PROPOSED SOC FREQUENCY SYNTHESIZER ARCHITECTURE	- 15 -
CHAPTER 2    3RD ORDER PLL MODEL	- 17 -
2.1	PLL LINEAR MODEL	- 17 -
2.2	REFERENCE CLOCK	- 19 -
2.3	PFD AND CHARGE PUMP	- 22 -
2.4	3RD ORDER LOW PASS FILTER	- 24 -
2.5	DIFFERENTIAL VCO	- 25 -
2.6	PROGRAMMABLE DIVIDER	- 26 -
2.7	FRACTIONAL-N FREQUENCY DIVIDER	- 29 -
CHAPTER 3    SOC PLL ARCHITECTURE	- 33 -
3.1	PROPOSED PLL STRUCTURE AND MODULES	- 33 -
3.2	REFERENCE CLOCK SELECTION	- 34 -
3.3	PFD	- 35 -
3.4	CHARGE PUMP	- 37 -
3.5	LOW PASS FILTER	- 38 -
3.6	DIFFERENTIAL VCO	- 41 -
3.7	HIGH PERFORMANCE FREQUENCY DIVIDER	- 44 -
3.8	PSEUDO FRACTIONAL-N DIVIDER	- 47 -
CHAPTER 4    PHASE SELECT ALGORITHM	- 51 -
4.1	X86-BASED PC CLOCK DOMAIN	- 51 -
4.2	FREQUENCY AND PHASE SELECTION ALGORITHM	- 52 -
4.3	TWO PLLS BASED FREQUENCY SYNTHESIZER ARCHITECTURE	- 54 -
CHAPTER 5    POST SIMULATION AND TEST PLAN	- 58 -
5.1	PROGRAMMABLE INTEGER DIVIDER SIMULATION	- 58 -
5.2	DIFFERENTIAL VCO SIMULATION	- 59 -
5.2.1	Bias circuit optimization	- 59 -
5.2.2	Differential VCO simulation	- 61 -
5.3	PSEUDO FRACTIONAL-N DIVIDER SIMULATION	- 63 -
5.4	COMPLETE CIRCUIT SIMULATION	- 64 -
5.5	SPECIFICATION COMPARISON	- 65 -
5.6	PROTOTYPE LAYOUT AND BONDING DRAWING	- 66 -
5.7	SCHEMATIC AND MEASUREMENT PLAN	- 68 -
5.7.1	Schematic	- 68 -
CHAPTER 6    CONCLUSION	- 70 -
6.1	FUTURE RESEARCH	- 71 -
REFERENCE MATERIALS         -72-
Appendix                    -73-

LIST OF FIGURES

FIGURE 1. 1   ARM BASED SOC BLOCK DIAGRAM [1]	- 2 -
FIGURE 1. 2    MODERN INTELR X86 PC PLATFORM STRUCTURE [2]	- 3 -
FIGURE 1. 3   ARM-BASED PORTABLE DEVICES	- 4 -
FIGURE 1. 4   SOC TECHNOLOGY TREND	- 5 -
FIGURE 1. 5   INTELR X86-BASED PC ARCHITECTURE IN [4]	- 6 -
FIGURE 1. 6   NB AND SB INTEGRATED SOLUTION [5]	- 7 -
FIGURE 1. 7   X86-BASED PC BLOCK DIAGRAM AND BUS CLOCK	- 9 -
FIGURE 1. 8   INTEL CPU C-STATE CHART	- 10 -
FIGURE 1. 9   PC CLOCK SCHEME AND PLLS LOCATION	- 11 -
FIGURE 1. 10   PEX PHY BLOCK EXAMPLE AND INTERNAL CLOCK	- 13 -
FIGURE 1. 11  EXAMPLES OF DIFFERENT REFERENCE CLOCK IN PEX PHY	- 14 -
FIGURE 1. 12   PROPOSED SOC FREQUENCY SYNTHESIZER BLOCK DIAGRAM	- 16 -

FIGURE 2. 1  LINEAR PLL MODEL IN [6].	- 18 -
FIGURE 2. 2   3RD ORDER CHARGE-PUMP-BASED PLL BLOCK IN [6]	- 19 -
FIGURE 2. 3   COMMON X’TAL CIRCUIT	- 20 -
FIGURE 2. 4  PFD AND CHARGE PUMP STRUCTURE	- 22 -
FIGURE 2. 5   STATE DIAGRAM OF PFD	- 23 -
FIGURE 2. 6  THE TRANSFER FUNCTION CURVE OF CHARGE PUMP	- 24 -
FIGURE 2. 7   3RD CHARGE-PUMP-BASED PLL MATHEMATICAL MODEL	- 24 -
FIGURE 2. 8   THE FOUR-STAGE DIFFERENTIAL VCO STRUCTURE.	- 26 -
FIGURE 2. 9   CMOS PROGRAMMABLE DIVIDE-BY-N COUNTER	- 27 -
FIGURE 2. 10   NEW EOC CIRCUIT OF DIVIDE-BY-N COUNTER IN [9]	- 27 -
FIGURE 2. 11   THE TIMING OF A CONVENTIONAL DIVIDE-BY-N COUNTER.	- 28 -
FIGURE 2. 12   THE NEW CONCEPT OF CLOCK GENERATOR WITH FOUR-STAGE VCO IN [11].	- 30 -
FIGURE 2. 13   THE CIRCUIT OF   CLOCK GENERATION IN [11].	- 32 -

FIGURE 3. 1   MODULUS SOC PLL BLOCK DIAGRAM	- 33 -
FIGURE 3. 2   MODIFIED PDF IN [7].	- 36 -
FIGURE 3. 3   PRE-CHARGE REGISTER IN [7].	- 36 -
FIGURE 3. 4   CHARGE PUMP IN [7].	- 37 -
FIGURE 3. 5   UNITY-GAIN BANDWIDTH/ZERO LOCATION RATIO	- 39 -
FIGURE 3. 6   SETTLING TIME VS. PHASE MARGIN	- 40 -
FIGURE 3. 7   EIGHT STAGES DIFFERENTIAL VCO STRUCTURE	- 42 -
FIGURE 3. 8   DELAY CELL FOR PROPOSED VCO	- 42 -
FIGURE 3. 9   THE BIAS GENERATOR CIRCUIT IN [8]	- 43 -
FIGURE 3. 10   DIFFERENTIAL BUFFER	- 43 -
FIGURE 3. 11   MODIFIED RELOAD CIRCUIT IN [9]	- 44 -
FIGURE 3. 12   PROPOSED ECO CIRCUIT AND RELOAD METHODOLOGY	- 45 -
FIGURE 3. 13   COUNTER WAVEFORM ON THE PROPOSE COUNTER	- 45 -
FIGURE 3. 14    MODIFIED 6 BITS COUNTER	- 46 -
FIGURE 3. 15   MODIFIED 6 BITS ECO CIRCUIT	- 46 -
FIGURE 3. 16   6 BITS COUNTER WAVEFORM	- 46 -
FIGURE 3. 17   FLIP-FLOPS IN PSEUDO FRACTIONAL-N DIVIDER	- 47 -
FIGURE 3. 18    8/15 WAVEFORM GENERATE CIRCUIT	- 48 -
FIGURE 3. 19   WAVEFORM OF A GLOBAL RESET	- 48 -
FIGURE 3. 20   WAVEFORM WITHOUT JITTER	- 49 -
FIGURE 3. 21    4/5 (CK45) CLOCK GENERATION CIRCUIT	- 49 -
FIGURE 3. 22   PROPOSED TSPC CIRCUIT WITH SET/RESET	- 50 -

FIGURE 4. 1   COMPLETE TWO PLLS BASED SYNTHESIZER STRUCTURE	- 55 -

FIGURE 5. 1   MAXIMUM OPERATION SPEED COMPARE OF INTEGER DIVIDERS	- 59 -
FIGURE 5.2   VCO BIAS INPUT AND OUTPUT VOLTAGE (PRE SIM)	- 60 -
FIGURE 5. 3   VCO “RING” LAYOUT	- 62 -
FIGURE 5. 4   VCO DIFFERENTIAL OUTPUT VOLTAGE (POST-SIM.)	- 62 -
FIGURE 5. 5   JITTER PERFORMANCE COMPARE	- 63 -
FIGURE 5. 6   PLLS SETTLING STATUS	- 64 -
FIGURE 5. 7   PLL1 POST SIMULATION	- 65 -
FIGURE 5. 8    FULL CHIP LAYOUT AND BOND DIAGRAM	- 67 -
FIGURE 5. 9   MEASUREMENT SCHEMATICS	- 69 -
 
LIST OF TABLES
TABLE 1. 1   X86 PC PLATFORM BASIC CLOCK AND PLL GLANCE	- 12 -
TABLE 1. 2   SERDES INTERNAL CLOCK GLANCE	- 14 -

TABLE 2. 1   THE SYNTHESIZABLE PARAMETER AND ITS COMBINATION FOR 4-STAGE VCO	- 31 -

TABLE 3. 1   INPUT CLOCK SELECT FOR THE SOC FREQUENCY SYNTHESIZER	- 35 -

TABLE 4. 1   X86 PC CLOCK DOMAIN LIST	- 51 -
TABLE 4. 2   THE VBA MACRO SWEEP RESULT IN 1200MHZ	- 56 -
TABLE 4. 3   FREQUENCY COMBINATION RESULT	- 57 -

TABLE 5. 1   VCO START UP FREQUENCY AT CORNERS	- 61 -
TABLE 5. 2   PLL SPECIFICATION COMPARISON	- 66 -

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