本篇論文提出一種修改掃描鏈的方法，目的在於減少移動功率的消耗。利用本篇論文所提出的演算法不需要修改測試資料以及測試資料移入的順序，在掃描測試期間可以專注於降低移出功率的消耗。所提出的演算法步驟主要在於指定Response至合適的移出掃描鏈順序中，以降低測試資料在移出掃描鏈時的切換頻率。我們利用增加一個額外的控制訊號去切換掃描鏈的移入及移出模式。為了驗證所提出方法的有效性，我們實驗在ISCAS’89的六個大型測試基準電路上，實驗結果顯示，我們所提出的方法能有效地降低移動功率的消耗。

This paper presents a scan chain modification scheme aiming at minimizing scan-shift power in this paper. We focus on reducing the scan-out power during scan shift when using our algorithm without modification of test patterns and scan-in ordering. An algorithmic procedure for assigning responses in scan-out reordering reduces scan-out transitions. We only use an additional control signal to change scan-in mode and scan-out mode. To verify the effectiveness of the proposed technique, we conduct experiments on large ISCAS’89 benchmark circuits and the results show that our proposed technique significantly reduces test power consumption.

中文摘要	I 
英文摘要	II
內文目錄	III
圖片目錄	V
表格目錄	VI

第一章 序論	1
1.1 研究動機	1
1.2 低功率測試所帶來的挑戰	4
1.3 低功率測試技術	7
1.3.1 以APTG為基礎之技術	7
1.3.2 以DFT為基礎之技術	10
1.4 論文架構	13

第二章 研究背景	14
2.1 全掃瞄式架構	14
2.2 功率消耗與計算	17

第三章 提出的方法	19
3.1 提出的掃描架構	19
3.2 所提出演算法	22
3.2.1 決定測試資料	22

第四章 實驗結果	30

第五章 結論	36
5.1 結論與未來展望	36

REFERENCES	37

圖片目錄
圖 1.1掃描式設計	2
圖 1.2掃描測試時所產的移動功率與捕捉功率	3
圖 2.3在循序電路中要偵測一個定址錯誤其困難度	15
圖 2.4 (A) 一個 MUXED-D 的掃描細胞 (B) 掃描鏈式樣	15
圖 2.5常見的全掃描式電路	16
圖 2.6計算WEIGHTED TRANSITION COUNTS之範例	18
圖 3.7 SCAN CHAIN結構 (A)原始結構 (B)所提出修改的結構	20
圖 3.8所提出修改的SCAN CHAIN結構範例	21
圖 3.9流程圖	23
圖 3.10回傳值比較表之步驟	28
圖 3.11所提出的演算法之虛擬碼	29
圖 4.12使用0-FILLING之實驗結果	34
圖 4.13使用1-FILLING之實驗結果	34
圖 4.14使用RANDOM-FILLING之實驗結果	35
圖 4.15使用MT-FILLING之實驗結果	35

表格目錄
表 4.1實驗中的測試向量以及掃描正反器數量	30
表 4.2在ISCAS’89六個大型電路下所獲得的功率改善	32
表 4.3我們所提出的方法與[11]做比較	33

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