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系統識別號 U0002-0408201115164900
中文論文名稱 新式的掃描測試方案以降低移動功率消耗
英文論文名稱 A New Scan Scheme for Shifting Power Reduction
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 99
學期 2
出版年 100
研究生中文姓名 林助銓
研究生英文姓名 Chu-Chuan Lin
學號 698450391
學位類別 碩士
語文別 中文
口試日期 2011-07-12
論文頁數 39頁
口試委員 指導教授-饒建奇
委員-饒建奇
委員-李建模
委員-陳竹一
委員-梁新聰
中文關鍵字 掃描測試  低功率 
英文關鍵字 Scan Testing  Low Power 
學科別分類 學科別＞應用科學＞電機及電子
中文摘要 本篇論文提出一種修改掃描鏈的方法，目的在於減少移動功率的消耗。利用本篇論文所提出的演算法不需要修改測試資料以及測試資料移入的順序，在掃描測試期間可以專注於降低移出功率的消耗。所提出的演算法步驟主要在於指定Response至合適的移出掃描鏈順序中，以降低測試資料在移出掃描鏈時的切換頻率。我們利用增加一個額外的控制訊號去切換掃描鏈的移入及移出模式。為了驗證所提出方法的有效性，我們實驗在ISCAS’89的六個大型測試基準電路上，實驗結果顯示，我們所提出的方法能有效地降低移動功率的消耗。
英文摘要 This paper presents a scan chain modification scheme aiming at minimizing scan-shift power in this paper. We focus on reducing the scan-out power during scan shift when using our algorithm without modification of test patterns and scan-in ordering. An algorithmic procedure for assigning responses in scan-out reordering reduces scan-out transitions. We only use an additional control signal to change scan-in mode and scan-out mode. To verify the effectiveness of the proposed technique, we conduct experiments on large ISCAS’89 benchmark circuits and the results show that our proposed technique significantly reduces test power consumption.
論文目次 中文摘要 I
英文摘要 II
內文目錄 III
圖片目錄 V
表格目錄 VI

第一章 序論 1
1.1 研究動機 1
1.2 低功率測試所帶來的挑戰 4
1.3 低功率測試技術 7
1.3.1 以APTG為基礎之技術 7
1.3.2 以DFT為基礎之技術 10
1.4 論文架構 13

第二章 研究背景 14
2.1 全掃瞄式架構 14
2.2 功率消耗與計算 17

第三章 提出的方法 19
3.1 提出的掃描架構 19
3.2 所提出演算法 22
3.2.1 決定測試資料 22

第四章 實驗結果 30

第五章 結論 36
5.1 結論與未來展望 36

REFERENCES 37

圖片目錄
圖 1.1掃描式設計 2
圖 1.2掃描測試時所產的移動功率與捕捉功率 3
圖 2.3在循序電路中要偵測一個定址錯誤其困難度 15
圖 2.4 (A) 一個 MUXED-D 的掃描細胞 (B) 掃描鏈式樣 15
圖 2.5常見的全掃描式電路 16
圖 2.6計算WEIGHTED TRANSITION COUNTS之範例 18
圖 3.7 SCAN CHAIN結構 (A)原始結構 (B)所提出修改的結構 20
圖 3.8所提出修改的SCAN CHAIN結構範例 21
圖 3.9流程圖 23
圖 3.10回傳值比較表之步驟 28
圖 3.11所提出的演算法之虛擬碼 29
圖 4.12使用0-FILLING之實驗結果 34
圖 4.13使用1-FILLING之實驗結果 34
圖 4.14使用RANDOM-FILLING之實驗結果 35
圖 4.15使用MT-FILLING之實驗結果 35

表格目錄
表 4.1實驗中的測試向量以及掃描正反器數量 30
表 4.2在ISCAS’89六個大型電路下所獲得的功率改善 32
表 4.3我們所提出的方法與[11]做比較 33
參考文獻 [1] Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Devices,” in Proc. IEEE VLSI Test Symp. (VTS’93), Atlantic City, NJ, USA, Apr. 6-8, 1993, pp. 4-9.
[2] P. Girad, “Survey of Low-Power Testing of VLSI Circuits,” IEEE Design & Test of Computers, vol. 19, no. 3, May/June, 2002, pp. 82-92.
[3] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, San Francisco: Elsevier, 2006.
[4] K. J. Lee, T. C. Huang, and J. J. Chen, “Peak-power reduction for multiple-scan circuits during test application,” in Proc. IEEE Asian Test Symp. (ATS’00), Taipei, Taiwan, Dec. 4-6, 2000, pp.453-458.
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[6] S. Wang and S. K. Gupta, “ATPG for Heat Dissipation Minimization for Scan Testing,” in Proc. ACM/IEEE Design Auto. Conf. (DAC’97), New York, NY, USA, 1997, pp. 614-619.
[7] S. Chakravarty and V. Dabholkar, “Minimizing Power Dissipation in Scan Circuits during Test Application,” in Proc. IEEE Asian Test Symp. (ATS’94), Nara, Japan, Nov 15-17, 1994, pp. 51-56.
[8] P. Girard, C. Landrault, S. Pravossoudovitch and D.Severac, “Reducing Power Consumption during Test Application by Test Vector Ordering,” in Proc. Int’l Circuits and Systems Symp. (ISCAS’98), vol. 2, Monterey, CA, USA, May. 31-Jun. 3, 1998, pp. 296-299.
[9] P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “A Test Vector Ordering Technique for Switching Activity Reduction during Test Operation,” in Proc. Great Lakes Symp. on VLSI (GLS-VLSI’ 99), Ypsilanti, MI, USA, Mar. 4-6, 1999, pp. 24-27.
[10] R. Sankaralingam and N. A. Touba, "Controlling Peak Power during Scan Testing," in Proc. IEEE VLSI Test Symp. (VTS’02), Apr. 28-May. 2, 2002. pp.153-159.
[11] Y. Wu and M.C. Chao, "Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes", in Proc. IEEE VLSI Test Symp. (VTS’08), San Diego, CA, USA, Apr. 27-May. 1, 2008, pp.147-154.
[12] V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. M. Reddy, “Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits during Test Application,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 12, Dec. 1998, pp. 1325-1333.
[13] W.-D. Tseng, “Scan Chain Ordering Technique for Switching Activity Reduction during Scan Test,” IEE Proceedings on Computers and Digital Techniques, vol. 152, no. 5, Sept. 2005, pp. 609-617.
[14] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and A. Virazel, “Design of Routing-Constrained Low Power Scan Chains,” in Proc. Design Automation and Test in Europe conference and exhibition, Paris, France, Feb 16-20, 2004, pp. 62-67.
[15] L. Whetsel, “Adapting Scan Architectures for Low Power Operation,” in Proc. IEEE Int’l Test Conf. (ITC’00), Atlantic City, NJ, USA, Oct. 3-5, 2000, pp. 863-872.
[16] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, “A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores,” in Proc. IEEE Asian Test Symp. (ATS’01), Kyoto, Japan, Nov 19-21, 2001, pp. 253-258.
[17] T.-C. Huang and K.-J. Lee, “A Token Scan Architecture for Low-Power Testing,” in Proc. IEEE Int’l Test Conf. (ITC’01), Baltimore, MD, USA, Oct. 30-Nov. 1, 2001, pp 661-669.
[18] N. Nicolici and B. M. Al-Hashimi, “Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits,” IEEE Trans. Computers, vol. 51, no. 6, Jun. 2002, pp. 721-734
[19] K. J. Lee, T. C. Huang, and J. J. Chen, “Peak-power reduction for multiple-scan circuits during test application,” in Proc. IEEE Asian Test Symp. (ATS’00), Taipei, Taiwan, Dec. 4-6, 2000, pp.453-458.
[20] R. Sankaralingam and N. A. Touba, “Reducing test power during test using programmable scan chain disable,” in Proc. The First IEEE International Workshop on Electronic Design, Test and Applications. (DELTA’02), Christchurch, New Zealand, Jan. 29-31, 2002, pp.159-163.
[21] S. Gerstendorfer and H.-J. Wunderlich, “Minimized Power Consumption for Scan-Based BIST,” in Proc. IEEE Int’l Test Conf. (ITC’01), Atlantic City, NJ, USA Sept. 28-30, 1999, pp. 77-84.
[22] E. Alpaslan, Y. Huang, X. Lin, W.-T. Cheng, J. Dworak, “Reducing Scan Shift Power at RTL,” in Proc. IEEE VLSI Test Symp. (VTS’08), San Diego, CA, USA, Apr. 27-May. 1, 2008, pp. 139-146.
[23] R. Sankaralingam, R. R. Oruganti, and N. A. Touba. “Static Compaction Techniques to Control Scan Vector Power Dissipation,” in Proc. IEEE VLSI Test Symp. (VTS’00), Montreal, QC, Canada, Apr. 30-May. 4, 2000, pp. 35-40.
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