§ 瀏覽學位論文書目資料
  
系統識別號 U0002-0408201113470400
DOI 10.6846/TKU.2011.00131
論文名稱(中文) 使用選擇性X遮罩編碼去減少測試控制資料量的方法
論文名稱(英文) A New Method of A New Method of Reducing Testing Control Data Using the Selective of X-masking Coding
第三語言論文名稱
校院名稱 淡江大學
系所名稱(中文) 電機工程學系碩士班
系所名稱(英文) Department of Electrical and Computer Engineering
外國學位學校名稱
外國學位學院名稱
外國學位研究所名稱
學年度 99
學期 2
出版年 100
研究生(中文) 黃敬棠
研究生(英文) Jing-Tang Huang
學號 698450011
學位類別 碩士
語言別 繁體中文
第二語言別
口試日期 2011-07-12
論文頁數 32頁
口試委員 指導教授 - 饒建奇
委員 - 陳竹一
委員 - 李建模
委員 - 梁新聰
委員 - 饒建奇
關鍵字(中) X遮罩
關鍵字(英) X-masking
第三語言關鍵字
學科別分類
中文摘要
在傳統的測試方法上,從待測電路(CUT)壓縮測試輸出信號有兩種方法。其中一種方法多輸入簽名暫存器(MISR),已被使用了幾十年。但這個方法是不能有任何的X值進入MSIR。因此,在輸出端需要一個遮罩(mask)去處理X的值。傳統的X遮罩技術,需要很多的資料量加以控制,這些資料量占據了絕大部分的記憶體空間。而本文提出了一種選擇性的X遮罩的編碼,進一步減少了控制碼的資料量。在實驗結果中,掃描鏈反應(scan response)產生了更好的壓縮比(compression ratio),對於在較長而且X連續性較多的電路裡,減少控制碼的量越明顯,除此之外,此方法所使用的解壓縮硬體可以被運用在任何學術或業界電路中。
英文摘要
Traditionally, the circuit under test (CUT) compression test output signal in two ways. One way, multiple input signature register (MISR) has been used for decades. However, this method can not have any X value into the MSIR. Therefore, the output needs a mask to deal with the X value. Traditional X-mask technology needs a large number of data to control. This paper presents a selective encoding of X mask to further reduce the amount of data of control codes. In the experimental results, the scan response produced a number of better compression ratio (CR), For contain longer and more continuous X circuit, the amount of control code which are reduced more obvious, in addition, the extract hardware can be used in any academic or industry circuits.
第三語言摘要
論文目次
內文目錄
中文摘要..................I
英文摘要..................II
內文目錄..................III
圖片目錄..................V
表單目錄..................VI


第一章 序論....................1

1.1 研究背景..............1
1.2 壓縮測試所帶來的挑戰..2
1.3 X訊號處理的技術.......5
1.3.1 過去的技術..........5
1.3.2 現有的技術..........9

第二章 提出的解壓縮硬體及方法..12

2.1 解壓縮硬體架構........12
2.2 提出的解壓縮方法......13

第三章 提出的壓縮方法..........17

3.1 研究動機與想法........17
3.2 壓縮控制碼的演算法....19
3.2.1 定義壓縮狀態........19
3.2.2 壓縮控制碼..........21

第四章 實驗結果................27

第五章 結論....................29

References.....................30

圖片目錄 
圖1.1 測試壓縮架構	3
圖1.2 輸出響應偵錯概念圖	4
圖1.3 XOR TREE基本架構	7
圖1.4多輸入簽名暫存器(MISR)基本架構	8
圖1.5 X-masking基本架構	11
圖2.1 提出的解壓縮硬體架構	12
圖3.1 提出的壓縮程序圖	25
圖3.2 提出的壓縮流程圖	26

表單目錄
表1.1 非X容忍的XOR TREE範例	7
表1.2 輸入簽名暫存器(MISR)起始狀態為0000的範例	8
表1.3 X-masking範例	11
表3.1 控制狀態表	20
表3.2 在正常狀態下原始碼對控制碼的編碼例子	22
表3.3 原始碼未發現X項時對控制碼編碼的步驟	23
表3.4 控制碼編碼後結果不好時的步驟	23
表4.1 工業電路模擬結果	28
表4.2 學術電路模擬結果	28
參考文獻
[1]	L. Geppert, Technology 1998 analysis and forecast: Solid state, IEEE Spectr., 1998, Vol. 35, pp. 23-28.
[2]	L.-T. Wang, C.-W. Wu, and X. Wen, “VLSI Test Principles and Architectures”, Morgan Kaufmann, 2006.
[3]	M. Subhasish, M. Mitzenmacher, S. S. Lumetta, and P. Nishant, “X-Tolerant Test Response Compaction”, IEEE Design & Test of Computers, 2005, Vol. 22, pp. 566-574.
[4]	D. Czysz, G. Mrugalski, N. Mukherjee, J. Rajski, and J. Tyszer, “On Compaction Utilizing Inter and Intra-Correlation of Unknown States”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010, Vol. 29.
[5]	W. Chen, S.M. Reddy, I. Pomeranz, J. Rajski, and J. Tyszer, “On Compacting Test Response Data Containing Unknown Values”, IEEE Int’l Conference on Computer Design (ICCD), 2003, pp. 855-862.
[6]	T. Hiraide, Osei Boateng Kwame, H. Konishi, K. Itaya, M. Emori, H. Yamanaka, and T. Mochiyama, “BIST-aided scan test - a new method for test cost reduction”, in Proc. IEEE VLSI Test Symp. (VTS’03), 2003, pp. 359 – 364.
[7]	G. Mrugalski, N. Mukherjee, J. Rajski, D. Czysz, and J. Tyszer, “Highly X-Tolerant Selective Compaction of Test Responses,” in Proc. IEEE VLSI Test Symp. (VTS’09), 2009, pp. 245-250.
[8]	M. C.-T. Chao, S. Wang, S.T. Chakradhar, and K.-T.Cheng, “Response Shaper: A Novel Technique to Enhance Unknown Tolerance for Output Response Compaction”, IEEE Int’l Conference on Computer-Aided Design, 2005, pp. 80-87.
[9]	R. Garg, R. Putman, and N.A. Touba, “Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation”, in Proc. IEEE VLSI Test Symp. (VTS’08), 2008, pp. 35-42.
[10]	J. Rajski, and J. Tyszer, “Synthesis of X-tolerant convolutional compactors”, in Proc. IEEE VLSI Test Symp. (VTS’05), 2005, pp. 114-119.
[11]	B. Keller, S. Bhatia, T. Bartenstein, B. Foutz, and A. Uzzaman, “Optimizing Test Data Volume Using Hybrid Compression”, in Proc. IEEE Asian Test Symp. (ATS’08), 2008, pp. 157-162.
[12]	S. Wang, K.J. Balakrishnan, and W. Wei, “X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactors”, IEEE Trans. Computers, 2008, Vol. 57, pp. 978-989.
[13]	E.H. Volkerink, and S. Mitra, “Response compaction with any number of unknowns using a new LFSR architecture”, in Proc. ACM/IEEE Design Auto. Conf. (DAC’05), 2005, pp. 117.
[14]	J. Rajski, J. Tyszer, G. Mrugalski, W.-T. Cheng, N. Mukherjee, and M. Kassab, “X-Press: Two-Stage X-Tolerant Compactor with Programmable Selector”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, Vol. 27.
[15]	M. Sharma and W.-T. Cheng, “X-Filter: Filtering unknowns from compacted test responses”, in Proc. IEEE Int’l Test Conf. (ITC’05), 2005, pp. 1090-1098.
[16]	N. A. Touba, “X-cancelling MISR—an X-tolerant methodology for compacting output responses with unknowns using a MISR”, in Proc. IEEE Int’l Test Conf. (ITC’07), 2007.
[17]	Yinhe Han; Yu Hu; Huawei Li; Xiaowei Li; “Theoretic analysis and enhanced x-tolerance of test response compact based on convolutional code”, in Proc. ACM/IEEE Design Auto. Conf. (DAC’05), 2005, pp. 53-58.
[18]	S. Mitra, and K.S. Kim, “X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction”, in Proc. IEEE Int’l Test Conf. (ITC’02), 2002, pp. 311-320.
[19]	S. Mitra, and K.S. Kim, “X-Compact: An Efficient Response Compaction Technique”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004, vol. 23, pp. 421-432.
[20]	S. Mitra, S.S. Lumetta, and M. Mitzenmacher, “X-Tolerant Signature Analysis”, in Proc. IEEE Int’l Test Conf. (ITC’04), 2004, pp. 432-441.
[21]	C. Barnhart et al., “OPMISR: The Foundation for Compressed ATPG Vectors”, in Proc. IEEE Int’l Test Conf. (ITC’01), 2001, pp. 748-757.
[22]	H. Tang, et al., “On efficient X-handling using a selective compaction scheme to achieve high test response compaction ratios”, in Proc. Int’l  Conference on. VLSI Design, 2005, pp. 59-64.
[23]	K. K. Saluja, and M. Karpovsky, “Testing computer hardware through data compression in space and time”, in Proc. IEEE Int’l Test Conf. (ITC’83), 1983, pp. 83-88.
[24]	J. Rajski et al, “Convolutional compaction of test responses”, in Proc. IEEE Int’l Test Conf. (ITC’03), 2003, pp. 745-754.
[25]	Y. Tang et al., “X-Masking during Logic BIST and Its Impact on Defect Coverage”, IEEE Trans. VLSI Systems, 2006, vol. 14, pp. 193-202.
[26]	Naruse, M.; Porneranz, I.; Reddy, S.M.; Kundu, S.; “On-chip compression of output responses with unknown values using lfsr reseeding ”, in Proc. IEEE Int’l Test Conf. (ITC’03), 2003, pp. 1060-1068.
論文全文使用權限
校內
校內紙本論文立即公開
同意電子論文全文授權校園內公開
校內電子論文立即公開
校外
同意授權
校外電子論文立即公開

如有問題,歡迎洽詢!
圖書館數位資訊組 (02)2621-5656 轉 2487 或 來信