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系統識別號 U0002-0407201710301800
中文論文名稱 三維積體電路矽穿孔之內建自我測試與內建自我雙通道修復研究設計
英文論文名稱 Build-In Self-Test and Build–In Dual Channel Self Repair Design for TSV-based 3D IC
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士在職專班
系所名稱(英) Department of Electrical Engineering
學年度 105
學期 2
出版年 106
研究生中文姓名 簡堯彬
研究生英文姓名 Yao-Pin Chen
學號 704440188
學位類別 碩士
語文別 中文
口試日期 2016-06-19
論文頁數 52頁
口試委員 指導教授-饒建奇
委員-呂學坤
委員-施鴻源
中文關鍵字 內建修補  3D IC  內建檢測 
英文關鍵字 3D IC  BIST  BISR 
學科別分類 學科別應用科學電機及電子
中文摘要 本論文『三維積體電路矽穿孔之內建自我測試與內建自我雙通道修復研究設計』,針對三維積體電路(Three-Dimensional Integrated Circuit, 3D ICs)中的矽穿孔(Through Silicon Via, TSV)規劃設計一內建自我測試與自我雙通道修復的架構。三維積體電路主要是由使用矽穿孔來作為垂直方向的通道,矽穿孔常因製程中的失誤產生錯位錯誤(Misalignment)以及隨機錯誤(Random Defect),使得矽穿孔無法正確的傳遞訊號。本論文擬針對錯誤矽穿孔設計一內建自我修復架構,針對錯誤的矽穿孔做取代修復的動作,提升整體電路之良率。
英文摘要 This paper "the three-dimensional integrated circuit silicon perforation built-in self test and built-in double channel self repair design" for 3D ICs (Three-Dimensional Integrated Circuit 3D ICs) Through in Silicon Via, TSV planning and design a built-in self testing and self repair of double channel architecture. Three dimensional integrated circuit mainly by using silicon holes as vertical channels, often because of perforated silicon process fault dislocation error (Misalignment) and random error (Random Defect), which can not correctly transfer signal silicon perforation. This thesis intends to design an internal self repairing architecture for the wrong silicon perforation, which will replace the repair of the wrong silicon hole, and improve the overall circuit yield.
論文目次 目錄
第一章 緒論 1
1.1 引言 1
1.2 研究動機 2
1.3 組織架構 5
第二章 三維積體電路自我測試與修復以及電路技術 6
2.1 內建自我測試Bulit-in Self-Test (BIST) 6
2.2 內建自我修補Built-In Self-Repair (BISR) 9
第三章 三維積體電路製造技術 13
3.1 三維積體電路(3D IC) 13
3.1.1 矽通道Through-Silicon-Via (TSV) 15
3.1.2 三維積體電路製造技術 16
3.2 相關研究 21
3.3 BIST和BISR設計 24
3.3.1 故障模型 26
3.4 BIST的設計 29
3.4.1 故障檢測 30
3.5 BISR的設計 33
3.5.1 配置冗餘TSV 34
3.5.2 修復故障TSV的方法 35
3.6 雙通道內建修補 38
第四章 實驗結果 41
4.1 簡介 41
4.2 實驗方式 41
4.3 實驗數據 43
4.3.1 單通道BISR模擬數據 43
4.3.2 雙通道BISR模擬數據 44
4.4 實驗比較 45
第五章 結論與未來展望 46
5.1 結論 46
5.2 未來展望 46
參考文獻 47







圖表目錄
圖 1.1 晶片偏移和旋轉 2
圖 1.2 TSV上下層電氣模型 3
圖 1.3 2D IC中BIST和BISR設計的框圖 4
圖 2.1 BIST設計架構 7
圖 2.2 嵌入式RAM的MBISR方案 10
圖 2.3 一個8 * 8位的可修復RAM的概念圖,一個備用行一個備用列 11
圖 2.4 Fuse macro 指令概念圖 12
圖 3.1 2D IC推疊成3D IC 14
圖 3.2 TSV電氣模型 15
圖 3.3 矽穿孔製造過程 18
圖 3.4 Via-Last 19
圖 3.5 Via-Fist 19
圖 3.6 Via-Middle 20
圖 3.7 兩層之間的TSV 21
圖 3.8 3D IC TSV架構 22
圖 3.9 TSV的3D IC架構的BIST和BISR基本設計 24
圖 3.10 TSV的產量趨勢 25
圖 3.11 TSV的故障和電氣模型 27
圖 3.12 TSV的測試操作 28
圖 3.13 BIST架構電路設計 29
圖 3.14 BIST設計中的測試程序的操作 31
圖 3.15 BIST測試操作流程 32
圖 3.16 BISR的電路設計 33
圖 3.17 冗餘TSV的配置 34
圖 3.18 BISR的修補 36
圖 3.19 修補過程中的修補和交換動作 36
圖 3.20 BISR流程圖 37
圖 3.21 雙通道修補架構 38
圖 3.22 BISR雙通道流程圖 39
圖 4.1 單通道檢測波形 43
圖 4.2 單通道輸出電路 43
圖 4.3 雙通道檢測波形 44
圖 4.4 雙通道輸出電路 44
表 4.1 模擬結果差異 45

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