淡江大學覺生紀念圖書館 (TKU Library)
進階搜尋


下載電子全文限經由淡江IP使用) 
系統識別號 U0002-0309200713054000
中文論文名稱 光通訊接收器前端電路之設計
英文論文名稱 The Design of Receiver Front-End Circuits for Optical Communications
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 95
學期 2
出版年 96
研究生中文姓名 陳之皓
研究生英文姓名 Chih-Hao Chen
學號 693390170
學位類別 碩士
語文別 英文
口試日期 2007-07-27
論文頁數 82頁
口試委員 指導教授-江正雄
委員-鄭國興
委員-郭建宏
委員-黃弘一
委員-劉榮宜
委員-江正雄
中文關鍵字 轉阻放大器  限制放大器  光接收器 
英文關鍵字 Transimpedance amplifier  limiting amplifier  optical receiver 
學科別分類 學科別應用科學電機及電子
中文摘要 隨著多媒體資訊傳播時代的來臨,網際網路越來越普及,使用端對網路骨幹之資料擷取趨於頻繁,對網路頻寬之需求亦日益增加。由於光訊號具有頻寬高、不受電磁波干擾、低傳輸損失及系統可靠度高等的特性,光纖網路因此兼具寬頻及低損耗之優勢,再加上光電元件的技術日益成熟,光纖網路為當今公認寬頻傳輸之最佳媒介與未來網際網路骨幹之主流。此網路是以雷射二極體或發光二極體,經由光纖,將聲音、影像、或數據資料由發射端發送至接收端,接收端則是由光偵測器及其他相關電路所組成的,其傳收速率可達10 Gb/s。因此光纖通訊的未來極具潛力,值得加以研究及發展。另外,值得一提的是,即使已經有許多光纖接收器是使用較昂貴的特殊製程,例如GaAs,來實現,但由於現今製程技術的進步,使用CMOS製程來實現也是相當普遍的了。本論文的目標即是以TSMC 0.18-μm CMOS製程來完成一操作於1.8 V、 10 Gb/s的光通訊接收器前端電路,其中包含轉阻放大器(Transimpedance Amplifier)與限制放大器(Limiting Amplifier)。
本論文為應用在光纖通訊系統接收器之研究,主要為一般光纖通訊接收器類比前端電路常用的原理,包括開迴路(共閘極)轉阻放大器與利用主動回授架構設計之限制放大器的研究,其主要目標為製作一低功率、高傳輸速率及高頻寬的接收器類比前端電路。整體系統要求參考同步光纖網路(Synchronous Optical Network, SONET),符合SONET OC-192的規範(即10 Gb/s之資料速率)。為了在節省面積的條件下達到增加頻寬的目的,電路廣泛使用CMOS所組成的主動元件來取代大面積的被動元件如電感、電阻及電容。
轉阻放大器部份,因為光二極體的寄生電容會降低頻寬,所以我們設法降低輸入所看到的電阻值,因此我們使用了共閘極的輸入級之轉阻放大器。另外,為了額外降低輸入阻值,我們在輸入端加了Regulated Cascode架構的電路。頻寬方面,我們使用了主動電感來增加頻寬,並且在增益級使用了交叉式主動回授(Itersecting Active Feedback)架構來額外增加頻寬。在1.8 V的操作電壓下,轉阻放大器提供了56 dBΩ的轉阻增益及8.27 GHz的-3dB頻寬。
限制放大器方面,為了達到目標的頻寬,我們使用了三階主動回授的架構來提高頻寬,並用交錯式主動回授(Interleaving Active Feedback)的方式來維持平坦增益。在1.8 V的操作電壓下,限制放大器提供了44.5 dB的差動電壓增益及10.3 GHz的-3dB頻寬。
英文摘要 With the advent of multimedia age, the internet is more and more popular. And with the growth of the number of internet users, the demanded volume of data transported over the internet backbone has increased. Thanks to that the light signal has the characteristics such as wide bandwidth, immunity against electromagnetic interference, low transmission loss, and high security, the fiber optics have the advantages including low loss and high bandwidth. With the increasing maturity of the technology of photoelectric devices, optical fiber has been acknowledged as the most appropriate medium for wideband transmission and a trend for internet backbone in the future. In fiber optics, The receiver end is made by a photo detector and the corresponding receiver circuits. The highest bit rate of fiber optics can reach 10 Gb/s. Therefore, the fiber optics has great potential in the future and is worth researching and developing. Furthermore, it is worth mentioning that conventional optical receivers are implemented in expensive process such as GaAs process. Even so, with the blooming progress of nowadays process technology, it is popular to implement transceiver circuits in CMOS process. This thesis presents some circuit techniques for the optical receiver front-end design with TSMC 0.18-μm CMOS process. The goal of this research is to realize a single-chip receiver front end, including a transimpedance amplifier and a limiting amplifier, with a 1.8-V supply for 10-Gb/s applications.
In this thesis, we do the research of the receiver for the application in fiber optical communication systems. The research mainly contains the concepts of the analog front-end circuits in a general fiber optical receiver, which includes an open-loop (common gate) transimpedance amplifier and a limiting amplifier with active feedback. The major goal is to design a low power, high transmission rate, and high bandwidth analog front-end circuit. The specification of the entire system refers to the Synchronous Optical Network (SONET). All circuits are designed to meet the 10 Gb/s data rate for SONET OC-192 standard. In order to extend the bandwidth and save the size area at the same time, the circuits extensively use the CMOS active devices in place of large passive ones such as inductors, resistors, and capacitors.
In the part of the transimpedance amplifier, since the parasitic capacitance of the photodiode will reduce the bandwidth, we have to think up a method to lower the input impedance. Thus, a common-gate input stage is used. Besides, in order to further lower the input impedance, we add a Regulated Cascode circuit. In bandwidth, we use the active-inductor peaking technique. Also, we employ the intersecting active feedback in the gain stage to further increase the bandwidth. With a 1.8-V supply, the transimpedance amplifier provides a transimpedance gain of 56 dBΩ with a –3-dB bandwidth of 8.27 GHz.
For the limiting amplifier, in order to fit the objective bandwidth, we use the third-order gain stages with active feedback. Furthermore, we employ the interleaving active feedback technique to restrain the gain peaking. With a 1.8-V supply, the limiting amplifier provides a differential voltage gain of 44.5 dB with a –3-dB bandwidth of 10.3 GHz.
論文目次 CONTENTS

Acknowledgements
Abstracts I
CONTENTS V
LIST OF FIGURES VII
LIST OF TABLES X

CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Protocols 3
1.3 Thesis Outline 4

CHAPTER 2 BACKGROUND AND BASIC CONCEPTS 6
2.1 Background 6
2.1.2 Sensitivity, Bit Error Rate, and Noise 6
2.1.2 Intersymbol Interference, Jitter, and Eye Diagram 12
2.2 Optical Transceiver Structure 17
2.3 Optical Receiver Front End 18
2.3.1 Photo Detectors 19
2.3.2 Transimpedance Amplifiers 21
2.3.3 Limiting Amplifiers 27
2.4 Specifications of the Receiver Front-End Circuits 33
2.4.1 Sensitivity and Noise 34
2.4.2 Gain 35
2.4.3 Bandwidth 36
CHAPTER 3 TRANSIMPEDANCE AMPLIFIERS 37
3.1 Introduction 37
3.2 Topologies 38
3.2.1 Open-Loop TIAs 39
3.2.2 Feedback TIAs 41
3.3 Circuit Design 43
3.3.1 Transimpedance Amplifier Core 44
3.3.2 Gain Stage 48
3.3.3 Single-to-Differential Conversion 53
3.4 Simulation Results 54

CHAPTER 4 LIMITING AMPLIFIERS 56
4.1 Introduction 56
4.2 Topologies 57
4.2.1 Limiting Amplifiers 57
4.2.2 Automatic Gain Control Amplifiers 58
4.3 Circuit Design 59
4.3.1 Limiting Amplifier Core 60
4.3.2 Offset Cancellation 67
4.3.3 Output Buffer 70
4.4 Simulation Results 72

CHAPTER 5 CONCLUSION 76

BIBLIOGRAPHY 79


LIST OF FIGURES

Figure 1.1 Optical Communication System 2
Figure 2.1 (a) Emitted signals, (b) received signals with noise, (c) determined signals with a bit error 8
Figure 2.2 The probability of the distribution of binary signal with noise 9
Figure 2.3 The curve of BER vs. Q 11
Figure 2.4 Effect of low-pass filtering with (a) periodic input and (b) random input 13
Figure 2.5 (a) Absolute jitter, (b) cycle-to-cycle jitter 14
Figure 2.6 (a) Random binary waveform, (b) 0.2-ns segments of the sequence and corresponding eye diagram 15
Figure 2.7 Bellcore’ eye diagram mask for SONET 16
Figure 2.8 (a) Transmitter and (b) receiver 17
Figure 2.9 PIN diode structure 20
Figure 2.10 APD photodiode structure 21
Figure 2.11 Low-impedance open-loop preamplifier structure 22
Figure 2.12 High-impedance open-loop preamplifier structure 23
Figure 2.13 Transimpedance feedback preamplifier structure 24
Figure 2.14 Thermal noise of a MOSFET 25
Figure 2.15 Spectral densities of flicker noise and thermal noise 25
Figure 2.16 Response of an RC filter to random data 26
Figure 2.17 Eye closure as a function of normalized bandwidth 27
Figure 2.18 Role of an LA in a receiver front end 28
Figure 2.19 Cascade of N-Stage small-signal amplifiers 28
Figure 2.20 Normalized gain, bandwidth, and gain–bandwidth product vs. the number of stages for overall cascaded gain of 100 31
Figure 2.21 An amplifier (a) without and (b) with offset compensation 33
Figure 2.22 Receiver front end with gain/swing requirements for SONET OC-192 35
Figure 3.1 The role of a TIA in optical receiver 37
Figure 3.2 A simple resistive topology 38
Figure 3.3 Common-gate topology 39
Figure 3.4 (a) CG stage at low frequencies and (b) at high frequencies 40
Figure 3.5 Feedback TIA 41
Figure 3.6 Conceptual block diagram of the proposed TIA 43
Figure 3.7 (a) CG input stage and (b) RGC input stage 44
Figure 3.8 Voltage drop of (a) regular RGC input stage and (b) modified RGC input stage 45
Figure 3.9 (a) Inductor peaking realized with active device and (b) equivalent circuit of (a) 47
Figure 3.10 (a) Variation of Zin with frequency and (b) equivalent model with an inductor 48
Figure 3.11 (a) Block diagram and (b) circuit diagram of the third-order gain stages with active feedback 49
Figure 3.12 (a) Block diagram and (b) circuit diagram of the proposed third-order gain stages with intersecting active feedback 50
Figure 3.13 Simulated frequency response of the gain stages with and without active feedback 52
Figure 3.14 Overall circuit diagram of the proposed TIA 52
Figure 3.15 Single-to-differential conversion 53
Figure 3.16 Simulated frequency response of the proposed TIA 54
Figure 3.17 Simulated eye diagram for the proposed TIA with a 10-Gb/s PRBS input 54
Figure 3.18 Circuit layout of the proposed TIA 55
Figure 4.1 The role of a postamplifier in optical receiver 56
Figure 4.2 Conventional architecture of an LA 58
Figure 4.3 Conventional architecture of an AGC 58
Figure 4.4 Architecture of the proposed LA 60
Figure 4.5 Required GBWC as a function of the stage number N for AT = 40 dB and BWT = 10 GHz 61
Figure 4.6 (a) Block diagram and (b) structural model of a third-order gain cell with active feedback 62
Figure 4.7 Realization of the third-order gain cell with active feedback 63
Figure 4.8 (a) Two-stage third-order gain cells with active feedback and (b) two-stage third-order gain cells with interleaving active feedback 64
Figure 4.9 Realization of two-stage third-order gain cells with interleaving active- feedback architecture 64
Figure 4.10 Simulated frequency response of the two-stage gain cells with and without interleaving active feedback 66
Figure 4.11 Overall LA core realized with interleaving active feedback 66
Figure 4.12 Conceptual architecture of a feedback-type offset cancellation 67
Figure 4.13 DC wander due to long runs 68
Figure 4.14 Realization of offset subtractor and offset cancellation feedback loop 68
Figure 4.15 Active (a) resistor and (b) capacitor 69
Figure 4.16 (a) General differential pair and (b) fT doubler as an output buffer 70
Figure 4.17 Input capacitance of an fT doubler maintaining (a) same voltage gain and (b) same driving capability 72
Figure 4.18 Simulated frequency response of the proposed LA 73
Figure 4.19 Simulated eye diagram for the proposed LA with a 10-Gb/s PRBS input 73
Figure 4.20 Circuit layout of the proposed LA 73
Figure 4.21 (a) Environmental components in practical measurement and (b) equivalent models of the effects from (a) 74


LIST OF TABLES

Table 1.1 The data rates of SONET/SDH standards 3
Table 2.1 The specification parameter values in eye diagram mask 16
Table 2.2 The specifications of receiver front end 36
Table 3.1 The performance expressions of an open-loop TIA 41
Table 3.2 The performance expressions of a feedback TIA 43
Table 3.3 TIA performance summary 55
Table 4.1 Brief comparison of LAs and AGCs 59
Table 4.2 LA performance summary 74
Table 5.1 Performance comparison of 10-G/s TIAs 77
Table 5.2 Performance comparison of 10-G/s LAs 78
參考文獻 BIBLIOGRAPHY

[1] B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw Hill, 2003.
[2] S. Galal and B. Razavi, “40-Gb/s Amplifier and ESD Protection Circuit in 0.18-μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2389– 2396, Dec. 2004.
[3] D. J. Sterling, Jr., Technician’s Guide to Fiber Optics 3rd Edition, Delmar, 2000.
[4] 原榮, Fiber Optic Communication Systems Principles and Practices, New WCDP, 2004.
[5] H. H. Kim, S. Chandrasekhar, C. A. Burrus, Jr., and J. Bauman, “A Si BiCMOS Transimpedance Amplifier for 10-Gb/s SONET Receiver,” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 769–776, May. 2001.
[6] C. S. Liu, Design and Implementation of Analog Front-end Circuits for Optical Communication System, MS Thesis, NTU, 2003.
[7] Bellcore, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria, Technical Report TA-NWT-000253, Issue 6, Sept. 1990.
[8] Y. L. Cheng, 10 Gbps Optical Receiver Front-End Circuit Design, MS Thesis, NCU, 2003.
[9] R. G. Smith and S. D. Personick, “Receiver Design for Optical Fiber Communication System”, in Semiconductor Devices for Optical Communication 2nd Edition, New York: Spinger-Verlag, 1982.
[10] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001.
[11] R. P. Jindal, “Gigahertz-band high-gain low-noise AGC amplifiers in fine-line NMOS,” IEEE J. Solid-State Circuits, vol. 22, no. 4, pp. 512–521, Aug. 1987.
[12] P. C. Huang, Y. H. Chen, and C. K. Wang, “A 2-V 10.7-MHz CMOS Limiting Amplifier/RSSI,” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1474–1480, Oct. 2000.
[13] E. A. Crain and M. H. Perrott, “A 3.125 Gb/s Limit Amplifier in CMOS with 42 dB Gain and 1 μs Offset Compensation,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 443–451, Feb. 2006.
[14] H. Kim and J. Bauman, “A 12 GHz 30 dB Modular BiCMOS Limiting Amplifier for 10 Gb SONET Receiver,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2000, pp. 160–161, 453.
[15] E. S
論文使用權限
  • 同意紙本無償授權給館內讀者為學術之目的重製使用,於2010-09-03公開。
  • 同意授權瀏覽/列印電子全文服務,於2010-09-03起公開。


  • 若您有任何疑問,請與我們聯絡!
    圖書館: 請來電 (02)2621-5656 轉 2281 或 來信