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系統識別號 U0002-0307200914225900
中文論文名稱 新式的低捕捉功率掃描單元選擇和快速掃描測試
英文論文名稱 A Novel Gated Scan-Cell Scheme for Low Capture Power (LCP) in At-Speed Testing
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 97
學期 2
出版年 98
研究生中文姓名 江明穎
研究生英文姓名 Ming-Ying Chiang
學號 696450674
學位類別 碩士
語文別 英文
口試日期 2009-06-09
論文頁數 43頁
口試委員 指導教授-饒建奇
委員-李建模
委員-梁新聰
中文關鍵字 時脈閘控  掃描測試  低功率 
英文關鍵字 Clock gating  scan testing  low power 
學科別分類 學科別應用科學電機及電子
中文摘要 最近以來,在掃描測試上實現低功率一直是個挑戰。先前有許多的研究都是著重在降低移動功率,只有少部分的研究有考慮到捕捉功率。在捕捉測試結果時,大量的切換動作會產生電源電壓降,進而導致電路故障與測試良率損失。本篇論文將提出一種新的演算法,並配合時脈閘的技術來閘控部分的掃描元件以防止內部電路產生不必要的切換動作。這些掃描元件都被劃分為若干個群組;對於每一個測試向量而言,在捕捉期間只有一部分的群組會對測試結果做存取的動作。我們所提出方法對於錯誤涵蓋率與測試時間不會造成任何影響,只是會增加一小部分的電路面積。經由ISCAS’89測試電路的實驗結果可知捕捉功率平均可以減少將近40%並且而外的硬體面積大約為5.49%。
英文摘要 Recently, low power implementation is a great challenge in scan-based testing. Much previous research focused on shift power reduction, only a few papers took capture power into consideration. In capture mode, excessive IP-drop may occur due to the high switching activity thus lead to circuit malfunction and yield loss. In this paper, a new algorithm is proposed with using clock gating technique on a part of the scan cells to prevent the internal circuit from unnecessary transitions. These scan cells are divided into several exclusive scan groups. For each test vector, only a portion of the scan groups are activated to store the test response in single capture cycle. The proposed method can reduce the capture power dissipation without any influence on fault coverage or testing time, and with a little impact on circuit area. Experimental results for ISCAS’89 benchmark circuits show that the average capture power reduction in test sequence can be up to 40% and hardware overhead is approximately 5.49%.
論文目次 中文摘要.............................................. I
英文摘要.............................................. II
Table of Contents..................................... III
List of Figures....................................... IV
List of Tables................................................ V


CHAPTER 1 INTRODUCTION.......................................... 1

1.1 Motivation........................................ 1
1.2 The Challenges of Low Power Testing............... 3
1.3 Low Power Testing Techniques............................................ 5
1.3.1 ATPG-based...................................... 5
1.3.2 DFT-based....................................... 7

CHAPTER 2 BACKGROUND AND PRELIMINARIES................ 10

2.1 Full-Scan Architecture............................ 10
2.2 Power Dissipation and Power Issues................ 13

CHAPTER 3 PORPOSED METHODS............................ 17

3.1 Proposed Scan Architecture........................ 17
3.2 Proposed Scan cell Analyze........................ 19
3.2.1 Selecting the Scan Cell......................... 19
3.3Reduce the Gated Cells and Grouping................ 25

CHAPTER 4 EXPERIMENTAL RESULTS........................ 28

CHAPTER 5 CONCLUSIONS................................. 38

REFERENCES............................................ 39

Figure 1.1 Shift power and capture power during scan
testing.................................. 2
Figure 2.1 Difficulty of detecting stuck-at-faults in
a sequential circuit..................... 10
Figure 2.2 (a) A muxed-D scan cell (b) A sample scan
chain.................................... 11
Figure 2.3 Conventional full-scan designed circuit.. 12
Figure 2.4 Dynamic power dissipation in a CMOS logic
gate..................................... 14
Figure 2.5 Illustration of manufacturing yield loss. 16
Figure 3.1 Proposed scan architecture............... 17
Figure 3.2 Timing diagram........................... 18
Figure 3.3 The Output-selecting for fault f......... 19
Figure 3.4 The transitions between test vector and
test response............................ 20
Figure 3.5 The scan cells and corresponding position.20
Figure 3.6 Scan cell selecting...................... 21
Figure 3.7 Algorithm of appropriate scan cell select
ing...................................... 22
Figure 3.8 Flow chart of the scan cell selects
procedure................................ 24
Figure 3.9 The process of X signal produces......... 25
Figure 3.10 The process of control signal grouping... 26
Figure 3.11 The symbol selecting for control set..... 27
Figure 4.1 The diagram of power reduction for s5378. 31
Figure 4.2 The diagram of power reduction for s9234. 32
Figure 4.3 The diagram of power reduction for s13207.33
Figure 4.4 The diagram of power reduction for s15850.34
Figure 4.5 The diagram of power reduction for s38584.35
Figure 4.6 The diagram of power reduction for s38417.36

Table 4.1 The test vector and scan flip-flop in our
experimental.............................. 29
Table 4.2 Experimental result of the six large
benchmarks based.......................... 30
Table 4.3 The different size of GE and improved
percentage for s5378...................... 31
Table 4.4 The different size of GE and improved
percentage for s9234...................... 32
Table 4.5 The different size of GE and improved
percentage for s13207..................... 33
Table 4.6 The different size of GE and improved
percentage for s15850..................... 34
Table 4.7 The different size of GE and improved
percentage for s38584..................... 35
Table 4.8 The different size of GE and improved
percentage for s38417..................... 36
Table 4.9 Power improvement ratio and extra area
ratio..................................... 37
Table 4.10 The hardware overhead of ISCAS’89 six
large circuit............................. 37
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