本論文主要利用基因演算法分別針對高密度分波多工(DWDM)之光纖通訊網路之封包排程、IEEE802.16正交分頻多路存取(OFDMA)次通道化排程機制及高速電路板(HSPCB)抑制電源雜訊去耦合電容數量選取等三種不同的系統提出解決的方法。
第一部分，我們是以基因演算法的架構提出一種改良的、可實現於可規劃的邏輯陣列元件(FPGA)的封包排程硬體架構，利用這樣的架構可以提升高密度分波多工技術(DWDM)在封包排程當中找到最佳化排程的速度，以實際提升使用之光纖通訊網路之效率。
第二部份，我們提出一個使用基因演算法在IEEE802.16正交分頻多路存取(OFDMA)次通道化排程機制上的解決方案。此解決方法能快速地收斂且獲取多使用者傳輸的機制下，下傳鏈路次訊框的最短傳輸時間排列方式。並且設計及實現於可規劃的邏輯陣列元件(FPGA)的硬體架構，利用這樣的硬體架構來實現多使用者之傳輸狀況下，能獲得下傳鏈路次訊框的最短傳輸時間之排列方式，並提升其傳輸的效能與降低所花費的成本。
在高速印刷電路板設計上，電源雜訊干擾問題的解決可以採用加上去耦合電容來解決及採用電源層切割或隔離電源板層技術。所以第三部份我們使用基因演算法來預估最少需使用的去耦合電容數目，不僅可以節省成本及佈局面積，亦可降低經驗決定的因素。在此部分，我們首先探討四分之一波長開路短枝共振腔之量測技術，並獲得印刷電路板介質材料的介電係數及衰減係數。緊接著使用網路分析儀(VNA)及模擬軟體完成高速電路板的金屬電阻耗損係數、介電材質耗損係數及有效介電係數的萃取。我們利用獲取之參數建構完成電源板層的等效電路模型，可提供未來設計電源系統阻抗的參考，並進一步使用基因演算法及HSPICE模式化的計算方式完成抑制電源雜訊去耦合電容數量最佳化的選取。最後，我們亦探討電源隔離島及切割等常用之隔離技術來探討降低干擾的問題來源。

In this dissertation we mainly utilize the principle of Genetic Algorithm to find the solutions for the problems encountered in the following three systems: the Packet Scheduling in optical communication network systems with Dense Wavelength Division Multiplexing (DWDM); the sub-channelization scheduling mechanism in the IEEE 802.16 Orthogonal Division Multiplexing Access (OFDMA) system and the determination of the number of decoupling capacitors needed to mitigate the power source noise in the high speed printed circuit board (HSPCB).    
In the first part we base on the principle of Genetic Algorithm to propose an improved and realizable field programmable gate-array (FPGA) hardware architecture in the implementation of the Packet Scheduling problem. By simulating this architecture we can improve and find the optimal scheduling speed for the packet scheduling problem in the Dense Wavelength Division Multiplexing (DWDM) system to effectively improve the transmission efficiency when data is transmitted through of the optical communication network.
In the second part we propose to utilize the Genetic Algorithm to find the solution to the problem of sub-channelization scheduling in the IEEE802.16 Orthogonal Frequency Division Multiplexing Access (OFDMA) system. This solving method can be in the shortest time period to determine the scheduling of the transmission of downlink sub-frames under the criterion of converging fast and to acquiring the transmission of more users. We then describe the design procedure to propose an improved and realizable FPGA hardware architecture and then to utilize this architecture under the criterion of transmitting as many as users as possible to find in the shortest time period the scheduling of the transmission of downlink sub-frames and to improve the transmission efficiency and to reduce the system cost.      
In the high speed printed circuit board design it can implement two methods to solve the power-bus noise interference problem. One method is by adding decoupling capacitors in the circuit board and the other method is to adopt the technique of power bus isolation or power plane segmentation. In the third part of this dissertation we try to employ the Genetic Algorithm to estimate the minimum number of decoupling capacitors required in multilayer printed circuit board; it results in not only to reduce the system cost and to minimize the required circuit board layout area, but also to decrease the dependence on empirical experience in the selection of capacitors. In this part we first investigate the measurement technique of using a quarter- wavelength open stub resonator and to obtain the dielectric constant and the loss factor of the dielectric material. In the sequel we will use the vector network analyzer (VNA) and the simulation software to complete the measurement and calculation of the transmission line’s conductor loss, dielectric constant, the dielectric loss and the effective dielectric constant of the high speed circuit board. We then from the extracted parameters to build an equivalent circuit model of the power-bus layer and this equivalent circuit model can be employed in the future as a reference in the impedance design of the power bus system. We will further to exploit the Genetic Algorithm and the calculation method of the modularized HSPICE tool to optimize the number of decoupling capacitors required in the mitigation of the power source noise. We also investigate the commonly employed techniques such as the power isolation island and the segmentation in the reduction of the interference sources.

Chinese Abstract …………………….…………………………………….	I
English Abstract …………………………………………………....……...	III
Table of Contents ………………………………………………....……….	VI
List of Figures ……………………………………………..………..………	X
List of Tables …………………………………………………..…..………..	XIV
Chapter 1. Introduction	
	1.1	Study Motivation …………………………………..…..……..	01
	1.1.1	The Hardware Design for a Genetic Algorithm Accelerator for Packet Scheduling Problems ……..….	01
	1.1.2	Design and Implementation of Subchannelization Scheduler in IEEE 802.16 Broadband Wireless Access Systems …………………………………….……..….….	02
	1.1.3	The Migration of Power or Ground bounce Noise …………………………………..……….…...……	04
	1.1.4	Measurement of RF PCB Dielectric Properties and Losses ……………………………………….…...….…...	05
	1.2	Organization …………………………...………...….….....…..	06
Chapter 2.	The Hardware Design for a Genetic Algorithm Accelerator for Packet Scheduling Problems	
	2.1	Introduction …………………………………………...…...…..	09
	2.2	General Genetic Algorithm for Packet Scheduler ………………………………………………..…..….	11
	2.2.1	Definition ……………………………………..….……...	11
	2.2.2	The fitness function ……………………………...……..	13
	2.2.3	Implementation of the genetic algorithms ………..…..	14
	2.3	Hardware design for the genetic algorithm accelerator ………………………………………………..….....	14
	2.4	The description of functional blocks ………….…….…...	18
	2.4.1	Random generator ……………………..……..…...……	18
	2.4.2	Base generator ……………………………….......……..	18
	2.4.3	Generation counter ……………………….………….....	19
	2.4.4	Operator ...........................................................................	20
	2.4.5	Operation selector ………………………….…..………	22
	2.4.6	Fitness value and delta calculator ……………...….......	23
	2.4.7	Delta compare and encode ………………..……….…...	23
	2.4.8	Duplicate priority encode …………..…………....…….	24
	2.4.9	Abort priority encode ………………………….…..…...	25
	2.4.10	Exit generation …………………..…………..…...……..	25
	2.5	Matlab Simulation Results …………………………....……	25
Chapter 3.	Design and Implementation of Subchannelization Scheduler in IEEE 802.16 Broadband Wireless Access Systems	
	3.1	Introduction ……………………………………………………	28
	3.2	Scheduler Architecture Design ………………………..…..	30
	3.2.1	Subscriber Station Source Data ………………..……...	30
	3.2.2	Design FFTSS by Using a Genetic Algorithm ……..….	32
	3.3	Analysis and Implementation FFTSS …………..……….	39
	3.3.1	Analysis of FFTSS …………………………………..….	39
	3.3.2	Implementation of FFTSS …………………………..…	41
	3.4	Simulation Results ………………………………………..….	42
	3.4.1	Hardware Architecture of FFTSS ………………..……	42
	3.4.2	Co-simulation of FFTSS …………………………..…...	45
Chapter 4.	The Migration of Power or Ground Bounce Noise	
	4.1	Introduction ……………………………………………..……..	48
	4.2	By Using Genetic Algorithm in the Optimal Selection of Multilayer Power Bus Decoupling Capacitors ……..	50
	4.2.1	Simulation Method by Using Power/Ground Impedance ……………………………………..………..	50
	4.2.2	Genetic Algorithm: The Determination of Optimal Decoupling Capacitors ………………………..………..	56
	4.3	The Noise Mitigation Comparison between the Power Bus Isolation and the Power Plane Segmentation …………………………………………………..	66
	4.3.1	Bridges Interconnection …………………………..……	70
	4.3.2	The Noise Mitigation Due to Different Plane Gap Sizes ……………………………………………………..	73
	4.3.3	The Effect of Gap Shape on the Noise Mitigation …....	75
Chapter 5.	Measurement of RF PCB Dielectric Properties and Losses	
	5.1	Introduction ……………………………………..……………..	79
	5.2	Quarter-wavelength Open Stub Resonator Method …	81
	5.2.1	Formula and Measurement ……………………..……..	81
	5.2.2	Experimental Results and Discussion ……………..…..	84
	5.3	Using Vector Network Analyzer and EDA Tool ADS Method	 ……………………………………………………..…..	88
	5.3.1	Transmission Line Characteristics of a Lossy Microstrip …………………………………………..…...	90
	5.3.2	By Utilizing Optimized ADS’s Functionalities in the Measurement of Conductor Loss, Dielectric Loss and Effective Dielectric Constant ……………..……………	92
	5.3.3	The Measurement of PCB Conducting Coefficient by Using Momentum Program in ADS Simulation …..….	96
	5.3.4	Verification by Using a Quarter Wavelength Open Stub Resonator …………………………………….…...	98
Chapter 6.	Conclusions …………………..…………………..……….	100
Chapter 7.	Future work ……………………………..………..………	104
References ………………………………………………..…………..………	106

LIST OF FIGURES
Figure 1.1	The architecture of this dissertation ……………………………..	8
Figure 2.1	An example illustrates the packet scheduling problem in a star-based network ……………………………………..………....	10
Figure 2.2	The flow block diagram of the G-GAPS …………………....…...	11
Figure 2.3	An example presents a permutation to form a chromosome …………………………………………………….....	13
Figure 2.4	Hardware architecture for Genetic Algorithm Accelerator ……………………………………………………...…	16
Figure 2.5	Base Generator ................................................................................	19
Figure2.6	Generation Counter …………………………………..…………..	20
Figure2.7	Operator Function ………………………………………..……….	20
Figure 2.8	Crossover Operation …………………………………………..….	21
Figure 2.9	Mutation Operation ………………………………………..……..	21
Figure 2.10	Operation Selector Function ……………………………..………	22
Figure 2.11	Fitness Value and Delta Calculator ……………………….……..	23
Figure 2.12	Block of Delta Compare and Encode ………………….………...	24
Figure 2.13	Block of Duplicate Priority Encode ……………………….…….	24
Figure 2.14	Block of Abort Priority Encode ………………………….………	25
Figure 2.15	Block of Next Generation ………………………………..……….	26
Figure 2.16	Simulation result of packet scheduling using Matlab software ..	27
Figure 3.1	Functional Block Diagrams for Design and Simulation ……..…	33
Figure 3.2	Illustration of the Representation of a Chromosome …..……….	35
Figure 3.3	Illustration of Crossover (a) Before Crossover (b) After Crossover ……………………………………………..……………	37
Figure 3.4	Illustration of Mutation …………………………..………………	38
Figure 3.5	Relationship between Users and Generations …………..………	40
Figure 3.6	Hardware Architecture for Implementing Genetic Algorithm ...	42
Figure 3.7	ALTERA Stratix EP1S80 DSP Development Board ……..……..	43
Figure 3.8	Timing Sequence Diagrams for Processing 20 Users ….….…….	44
Figure 3.9	Simulation Platform …………………………………………..…..	46
Figure 3.10	Actual Simulation Platform …………………………....……..…..	46
Figure 3.11	Percentages of Packages Served …………………….……….…...	47
Figure 4.1	The Distributed Power Bus Plane Model Built with Two-dimensional Arrays of C’s, R’s, and L’s ……………..……..	53
Figure 4.2	The Equivalent Lumped Circuit of Power Bus Plane ………..…	53
Figure 4.3	Comparison Between the Measured Z21 of a 27cm x 15cm Printed Circuit Board in the Text with Those Simulated Z21 by Using Two Simulation Methods as Discussed ……………..…….	56
Figure 4.4	Power Bus Circuit with Decoupling Capacitor Inserted …….....	59
Figure 4.5(a)	Fitness Function Used in the Genetic Algorithm Optimization Search Method with 1Ω Target Impedance ………………..……	63
Figure 4.5(b)	Fitness Function Used in the Genetic Algorithm Optimization Search Method with 0.5Ω Target Impedance …………….….….	63
Figure 4.6(a)	The Simulation and Measurement results of Power Plane Impedance with or without Including the Designed Five Decoupling Capacitors with 1Ω Target Impedance ………..…...	64
Figure 4.6(b)	The Simulation result of Power Plane Impedance with or without Including the Designed sixteen Decoupling Capacitors with 0.5Ω Target Impedance …………………………….….……	64
Figure 4.7(a)	The Simulation Results of Power Plane Impedance with one of the Five Optimized Decoupling Capacitors Eliminated in the Genetic Algorithm Simulation Method …………………..……...	65
Figure 4.7(b)	The Measurement Results of Power Plane Impedance with one of the Five Optimized Decoupling Capacitors Eliminated in the Genetic Algorithm Simulation Method ……………………..…...	65
Figure 4.8	The Power Plane Test Board with Isolated Power Island ……....	67
Figure 4.9	S21 with Different Gap Size of Isolated Power Island ……..…...	68
Figure 4.10	S21 with Different Placement Locations of Isolated Power Islands ………………………………………………………..…….	69

Figure 4.11	The Board with Different Placement Locations of Isolated Power Islands …………………………………………..………….	70
Figure 4.12	Test Board with Bridge Interconnection ……………..………….	71
Figure 4.13	S21s with e=2mm, 5mm and 10mm ………………………..…….	72
Figure 4.14	S21s with c=29mm, 39mm and 49mm ………………..………….	73
Figure 4.15	Test Board with Gap Isolation in Power Plane ………..………...	74
Figure 4.16	S21s from Different Gap Sizes ……………………………..…….	75
Figure 4.17	Test Board with Straight Line, Triangular and Rectangular Gap Shapes …………………………………….……….………….	76
Figure 4.18	S21s of Three Different Gap Shapes ………………..……………	76
Figure 4.19	S11, S21, and S22 Curves of Straight Line Gap Shape ……..…..	77
Figure 4.20	S11, S21, and S22 Curves of Triangular Gap ……………..……..	77
Figure 4.21	S11, S21, and S22 Curves of Rectangular Gap …………..……...	78
Figure 5.1	Quarter-wavelength Open Stub Resonator Structure ……..……	80
Figure 5.2(a)	Measured S21 of the Quarter-wavelength Open Stub Resonator at 193MHz …………………………………………………..……..	83
Figure 5.2(b)	Expanded Scale of the Measured S21 of the Quarter-wavelength Open Stub Resonator at 193MHz …...……	83
Figure 5.3	A 600MHz Quarter Wavelength Open Stub Resonator …..…….	84
Figure 5.4	Loss Factor (α)of the Designed Resonant Frequencies,
200MHz Harmonic Resonant Frequencies, 400MHz Harmonic
Resonant Frequencies and 600MHz Harmonic Resonant
Frequencies ……………………………………………………….. 87
Figure 5.5 Test setup in a semi-anechoic room for the measurement of the
overall maximum radiated field of a parallel-plane structure … 88
Figure 5.6 The Maximum Radiation Field Strengths of the Fifth
Harmonic of the Designed 200MHz Resonant
Quarter-wavelength Resonator and the Designed 1GHz
Resonant Quarter-wavelength Resonator ………………….…… 88
Figure 5.7 The Lossy Trasmisssion Line Equivalent Circuit Model Built
Procedure by using VNA and Agilent’s ADS ……….…………... 89
Figure 5.8 Equivalent Circuit of a Transmission Line ………………...…… 91
Figure 5.9 10 cm Long Transmission Line ………………..………………… 93
Figure 5.10 The Measured S-parameter Values of a 10 cm Transmission
Line ………………………………………………………………... 93
Figure 5.11 Built Test Circuit Module for Transmission Line in Simulation
software ……………………………………………………….…... 94
Figure 5.12 Equivalent Circuit Outputs and Measured Results ………..…... 94
Figure 5.13 Conductor Loss ( cond . α ) and Dielectric Loss ( diel. α ) ………..…… 95
Figure 5.14 Measured Data and the Total Loss Resulting from the ADS
Simulation …………………………………………….…………... 96
Figure 5.15 Attenuation Loss between the Simulated and Measured Data at
the Maximum Operating Frequency 3 GHz and Ideal
Conductor is assumed in the Simulation …………………..……. 97
Figure 5.16 Attenuation Loss between the Simulated and Measured Data at
the Maximum Operating Frequency of 3 GHz and the
Conductivity is Set at 5x106(Siemens/m) in the Simulation …..... 97
Figure 5.17 Equivalent Circuit Module for Transmission Line Built from
ADS Software at Maximum Operating Frequency of 600
MHz ……………………………………………………………….. 98
Figure 5.18 Results of Measured (Blue) and Simulated (Red) Data ……..…. 99

LIST OF TABLES
Table 2.1 IO registers list and their descriptions …………………….....…….. 17
Table 3.1 Link Parameters ……………………………………………...…..….. 31
Table 3.2 Maximum Number of Users in Different Transmission
Conditions ……………………………………………………...…….. 32
Table 3.3 User’s Amount of Information and Their Corresponding Number
of Symbols ……………………………………………………......…... 34
Table 3.4 Sub-Channel Assignments for Users, from sub-channel 1 to
sub-channel 8, Based on the Outcomes of Random Number
Generator ………………………………...……………………….…... 35
Table 3.5 Convergent Rates in Various Generations ………………………..... 40
Table 3.6 Hardware Synthesized and Simulation Results ……………..……... 44
Table 3.7 Convergent Time and the Number of Symbols
Transmitted ………………………………………………………...… 44
Table 3.8 Simulated Transmission Results between the Ideal and FFTSS
Hardware System ……………………………...…………………….. 47
Table 4.1 The resulting 20 Decoupling Capacitors by using the Genetic
Algorithm Optimization Searching Method with 1Ω Target
Impedance ……………………………………...……….......………... 61
Table 4.2 The resulting 20 Decoupling Capacitors by using the Genetic
Algorithm Optimization Searching Method with 0.5Ω Target
Impedance …………………………………………...……………….. 62
Table 5.1 Statistics of the Dielectric Constant ………………………………… 84
Table 5.2 Statistics of the Loss Factor of Each of the 200MHz、400MHz and
600MHz Harmonic Resonant Frequencies ……………………...….86

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