近年來，隨著嵌入式系統的發展，使得微控制器被廣泛的使用在不同的應用上，例如：智慧型手機、掌上型電腦、多媒體裝置、自動化系統、機器人控制等。針對嵌入式系統所設計的微控制器，是以控制功能與整合能力為第一優先考量。一般而言，微控制器會整合多元的通訊串列(UART、SPI、I2C、Microwire和1-wire等)、並列週邊(EMI、LBI和PCI Bus等)及一般輸出入介面(GPIO)等功能。而基於易使用、低成本、高頻寬與高穩定等特性，使得乙太網路在特定應用上是較為可行的傳輸方式，例如：即時影音傳輸、虛擬網路會議、高速資料傳送。因此，具備嵌入式網路功能的乙太網路微控制器，將成為未來的發展趨勢。
目前國內的微控制器廠商在產品佈局方面，仍以8位元微控制器為主，其次為16位元。單就最典型的8位元微控制器MC8051，全球一年的出貨量就可高達33億顆。但由於傳統MC8051的程式記憶體(Program Memory)只有4K Byte、資料記憶體(Data Memory)只有128 Byte、4組I/O埠與內部單一匯流排等限制，使其操控性與擴充性一直無法被使用在複雜的網路控制上。
因此本篇論文主要的研究是在於改進MC8051的4組I/O埠與單一匯流排限制，並使其能夠實現低成本、易操控與高擴充之乙太網路微控制器。為此目的，我們提出MC8051的等待狀態、ramx Transfer Interface與Ethernet Transfer Interface之設計。透過MC8051的等待狀態之設計，使得等待狀態可以插入MC8051的時序中，並使其保持閒置。而ramx Transfer Interface之設計，使得MC8051外部資料記憶體模組的控制訊號與Avalon匯流排可以互相結合。藉由Avalon的同步與共享機制，使得MC8051可以實現同步化多重I/O之控制。而Ethernet Transfer Interface之設計，使得MC8051同步化多重I/O控制可以整合DM9000A乙太網路控制器，並實現其乙太網路之控制能力。根據封包處理速率之分析結果，可以發現對於家電控制、工業控制、自動化系統、遠端管理與環境監控等基本網路控制，並不會牽扯到過於複雜的封包交換程序。因此，經由我們的MC8051封包處理速率分析，我們的研究確實有其可行之處。

In recent years, with the process of embedded systems, microprocessors have been widely used on many applications such as smart phones, laptops, multi-media equipments, automatic control systems, robot controls, etc. For the microprocessors designed for embedded systems, it firstly considers the control capability and integration capability. In general, the microprocessor integrals many communication sequences (e.g., UART, SPI, I2C, Microwire, 1-wire), parallel peripherals (e.g., EMI, LBI, PCI Bus) and General Purpose I/O (GPIO). Ethernet network always is an applicable transmission method in certain applications such as real-time multi-media transfer, virtual network conference, high speed data transfer, etc. because of its easy to use, low cost, high bandwidth and high stability. In conclusion, the embedded Ethernet micro-controller is one of the future trends.
Nowadays, the 8 bits micro-controllers still are the main product in Taiwan, and the 16 bits micro-controllers are the second one. The most typical 8 bits micro-controller is MC8051, because it sells 3.3 thousand million ones averagely in one year. MC8051 owns program memory with 4k bytes, data memory with 128 Bytes, 4 sets I/O ports and one single bus, so it can never be used to the application of controlling internet.
Our search is to improve the limitation casing by the 4 sets I/O ports and one single bus in MC8051 and implement an Ethernet micro-controller which is low cost, easy to use and high adaptability. We proposed the Waiting State of MC8051 and two circuits called ramx Transfer Interface and Ethernet Transfer Interface, respectively. The waiting state can be inserted into the timing of MC8051 and keeps an idle state though the design of the Waiting State for MC8051. The control signals of external data memory model of MC8051 can be combined with Avalon bus though the design of ramx Transfer Interface. The synchronous and shared mechanism of Avalon allows MC8051 to realize synchronous and multiple I/O control. Then the synchronous and multiple I/O control can be integrated with DM 9000A Ethernet controller and realize the control capability of Ethernet through the design of Ethernet Transfer Interface. According to our analysis of packet processing rate, our contribution can be used to basic network control (e.g., electric appliances, industry control, automatic control systems, remote management, Environmental Monitoring) because it does not require too complicated packet handshake procedure. With our analysis of packet processing rate, we truly proposed a feasible study in some respects.

目錄
第一章 緒論                                             - 1-
1.1    前言                                             - 1-
1.2    動機與目的                                       - 2-
1.3    論文章節架構                                     - 4-
第二章 背景知識與相關研究                               - 5-
2.1    背景知識                                         - 5-
2.1.1  微控制器MC8051                                   - 5-
2.1.2  Avalon匯流排介面                                 -10-
2.1.3  DM9000A乙太網路控制器                            -15-
2.2    相關研究                                         -20-
2.2.1  基於矽智財的發展                                 -20-
2.2.2  基於Avalon匯流排的發展                           -21-
第三章 系統架構的軟硬體設計                             -23-
3.1    硬體設計架構                                     -23-
3.1.1  MC8051的等待狀態設計                             -23-
3.1.2  Avalon匯流排主端的ramx Transfer Interface設計	 -27-
3.1.3  Avalon匯流排從端的Ethernet Transfer Interface設計-31-
3.1.4  硬體架構整合                                     -35-
3.2    軟體設計架構                                     -37-
3.2.1  DM9000A的暫存器之讀取與寫入程序                  -37-
3.2.2  DM9000A的EEPROM之讀取與寫入程序                  -38-
3.2.3  DM9000A的PHY暫存器之讀取與寫入程序方式           -40-
3.2.4  DM9000A的驅動初始化程序                          -42-
3.2.5  DM9000A的封包傳送程序                            -43-
3.2.6  DM9000A的封包接收程序                            -45-
第四章 實驗環境及實驗結果與分析                         -48-
4.1    實驗環境                                         -48-
4.2    實驗結果與分析                                   -51-
4.2.1  硬體開發的資源分析                               -51-
4.2.2  MC8051的等待狀態分析                             -54-
4.2.3  MC8051的封包處理速率分析                         -63-
第五章 結論與未來展望                                   -67-
參考文獻                                                -69-


圖目錄
圖1.1 嵌入式乙太網路的設計方式[1]                       - 3-
圖2.1 MC8051的核心區塊圖[2]                             - 6-
圖2.2 MC8051 IP Core的核心區塊圖[4]                     - 8-
圖2.3 MC8051 IP Core的階層式設計圖[3]                   - 8-
圖2.4 Avalon匯流排的系統連結架構圖[5]                   -10-
圖2.5 傳統匯流排的傳輸方式[6]                           -12-
圖2.6 Avalon匯流排的傳輸方式[6]                         -12-
圖2.7 DM9000A的內部區塊圖[8]                            -15-
圖2.8 處理器介面的訊號連接圖[8]                         -16-
圖2.9 8位元處理器介面的電路示意圖[8]                    -18-
圖2.10 CMD訊號與處理器介面之訊號連接圖[8]               -19-
圖2.11 ram_fct的架構[10][11]                            -21-
圖3.1 MC8051外部資料記憶體的讀取指令之等待流程圖        -25-
圖3.2 MC8051外部資料記憶體的寫入指令之等待流程圖        -26-
圖3.3 ramx Transfer Interface的內部架構圖               -28-
圖3.4 ramx Transfer Interface的電路符號圖               -29-
圖3.5 Ethernet Transfer Interface的內部架構圖           -32-
圖3.6 Ethernet Transfer Interface的電路符號圖           -33-
圖3.7 系統架構之硬體整合圖                              -36-
圖3.8 DM9000A封包傳送緩衝區的位址範圍圖[8]              -43-
圖3.9 DM9000A封包接收的訊框圖[8]                        -45-
圖4.1 DE2-70多媒體開發平台的外觀圖[18]                  -50-
圖4.2 DE2-70多媒體開發平台的區塊圖[18]                  -50-
圖4.3 硬體編譯的結果圖                                  -52-
圖4.4 硬體開發的資源圖                                  -53-
圖4.5 MC8051外部資料記憶體的讀取指令之Avalon匯流排主端訊號圖						 -57-
圖4.6 MC8051外部資料記憶體的讀取指令之Avalon匯流排從端訊號圖						 -58-
圖4.7 MC8051外部資料記憶體的寫入指令之Avalon匯流排主端訊號圖						 -61-
圖4.8 MC8051外部資料記憶體的寫入指令之Avalon匯流排從端訊號圖						 -62-
圖4.9 MC8051時脈計數器之封包接收開始訊號圖              -64-
圖4.10 MC8051時脈計數器之封包接收結束訊號圖             -65-
圖4.11 MC8051時脈計數器之封包傳送開始訊號圖             -66-
圖4.12 MC8051時脈計數器之封包傳送結束訊號圖             -66-


表目錄
表2.1 MC805 IP Core的訊號說明表[3]                      - 9-
表2.2 Avalon匯流排主端的訊號說明表[6]                   -13-
表2.3 Avalon匯流排從端的訊號說明表[6]                   -14-
表2.4 處理器介面之訊號說明表[8]                         -17-
表3.1 ramx Transfer Interface的內部架構說明表           -29-
表3.2 ramx Transfer Interface的電路符號之訊號說明表     -30-
表3.3 Ethernet Transfer Interface的內部架構說明表       -33-
表3.4 Ethernet Transfer Interface的電路符號之訊號說明表 -34-
表4.1 MC8051外部資料記憶體的讀取與寫入指令之訊號說明表  -54-
表4.2 MC8051時脈計數器之訊號說明表                      -63-

參考文獻

[1]	高速8位元網路MCU興起 [Online]. Available: http://www.asix.com.tw/Network_MCU_CT.htm
[2]	Jaka Simsic and Simon Teran. (Aug. 14, 2001). 8051 Core Specification (Rev. 0.1) [Online]. Available: http://opencores.org
[3]	Oregano Systems. (June 2002). MC8051 IP Core User Guide (Ver. 1.1) [Online]. Available: http://www.oregano.at/
[4]	Oregano Systems. (June 2002). MC8051 IP Core Overview (Ver. 1.2) [Online]. Available: http://www.oregano.at/
[5]	Altera Corporation. (Mar. 2008). Avalon Interface Specifications (Ver. 1.0) [Online]. Available: http://www.altera.com
[6]	李世安, 即時目標影像追蹤之SoPC設計. 臺北縣: 淡江大學電機工程學系博士班博士論文, 2008.
[7]	Xu Xing, Chen Zezong, Jiang Jing, and Ke Hengyu, “Porting from Wishbone Bus to Avalon Bus in SoC Design,” in Proc. International Conference on Electronic Measurement and Instruments (ICEMI’07), Xian, China, Aug. 16-July 18, 2007. pp. 1-862-1-865.
[8]	Davicom Semiconductor Inc. (Apr. 22, 2005). DM9000A 16/8 Bit Ethernet Controller with General Processor Interface APPLICATION NOTES (Ver. DM9000A-AN-V120) [Online]. Available: http://www.davicom.com.tw
[9]	Davicom Semiconductor Inc. (Apr. 21, 2005). DM9000A Ethernet Controller with General Processor Interface DATA SHEET (Ver. DM9000A-DS-P03) [Online]. Available: http://www.davicom.com.tw
[10]	Liu Limin, “A Prototyping IP Hardware for SOPC with Single Instruction Driving,” in Proc. International Conference on Communications, Circuits and Systems (ICCCAS’06), vol. 1, Guilin, China, June 25-28, 2006, pp. 559-562.
[11]	Limin Liu, “A Prototyping IP for Mobile Computing SOC,” in Proc. International Conference on Human System Interactions (HSI’08), Krakow, Poland, May 25-27, 2008, pp. 24-27.
[12]	Limin Liu, “A Reconfigurable SoPC Based on HW-SW Co-design,” in Proc. IEEE International Conference on Industrial Technology (ICIT’08), Chengdu, China, Apr. 21-24, 2008, pp. 1-4.
[13]	Feng Lin, Haili Wang, and Jinian Bian, “HW/SW Interface Synthesis based on Avalon Bus Specification for Nios-oriented SoC Design,” in Proc. IEEE International Conference on Field-Programmable Technology (FPT’05), Singapore, Dec. 11-14, 2005, pp. 305-306.
[14]	Chia-Ying Tseng and Yen-Chih Chen, “Design and Implementation of Multiprocessor System on a Chip (MPSoC) Based on FPGA,” in Proc. International Computer Symposium (ICS’08), Taipei County, Taiwan, Nov. 13-15, 2008.
[15]	Yang Xu and Min Xiang, “Design a New Type PWM Peripherals in Nios II,” in Proc. World Congress on Computer Science and Information Engineering (CSIE’09), vol. 2, Los Angeles, CA, Mar. 31-Apr. 2, 2009, pp. 442-446.
[16]	Altera DE2-70 多媒體開發平台 [Online]. Available: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=Taiwan&CategoryNo=58&No=230
[17]	DE2-70 Development and Education Board [Online]. Available: http://university.altera.com/materials/boards/de2_70/?hdl=Verilog&board=DE2&quartusII=9.0
[18]	Terasic Technologies Inc. (2007). DE2-70 Development and Education Board User Manual (Ver. 1.01) [Online]. Available: http://www.terasic.com
[19]	陳信源, Verilog硬體描述語言數位電路設計實務. 臺北市: 儒林圖書有限公司, 2005.
[20]	盧毅, 賴杰, VHDL與數位電路設計. 臺北市: 文魁資訊股份有限司, 2000.
[21]	陳慶逸, 林柏辰, VHDL數位電路學習與專題研究. 臺北市: 文魁資訊股份有限公司, 2005.
[22]	蔡栢樟, 視窗51模擬實務.C語言篇. 臺北市: 知行文化事業股份有限公司, 2000.
[23]	蔡朝洋, 單晶片微電腦8051/8951原理與應用. 臺北市: 全華科技圖書股份有限公司, 2005.
[24]	李世安, 自主移動機器人之定位系統與路徑規劃的設計. 臺北縣: 淡江大學電機工程學系碩士班碩士論文, 2004.
[25]	Damjan Lampret, Chen-Min Chen, Marko Mlinar, Johan Rydberg, Matan Ziv-Av, Chris Ziomkowski, Greg McGary, Bob Gardner, Rohit Mathur, and Maria Bolado. (Apr. 5, 2006). OpenRISC 1000 Architecture Manual (Rev. 1.3) [Online]. Available: http://http://opencores.org
[26]	Damjan Lampret. (Sep. 6, 2001). OpenRISC 1200 IP Core Specification (Rev. 0.7) [Online]. Available: http://opencores.org
[27]	Limin Liu, “A Dynamically Reconfigurable SOC,” in Proc. IEEE International Conference on Industrial Technology (ICIT’08), Chengdu, China, Apr. 21-24, 2008, pp. 1-4.
[28]	Kok-Leong Chang and Bah-Hwee Gwee, “A low-energy low-voltage asynchronous 8051 microcontroller core,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS’06), Island of Kos, GR, May 21-24, 2006, pp. 3181-3184.
[29]	Je-Hoon Lee, Young Hwan Kim, and Kyoung-Rok Cho, “A Low-Power Implementation of Asynchronous 8051 Employing Adaptive Pipeline Structure,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, vol. 55, no. 7, pp. 673-677, July 2008.
[30]	Chang-Jiu Chen, Wei-Min Cheng, Tuan-Chieh Wang, Yuan-Teng Chang, and Hung-Yue Tsai, “Instruction Decoder Implemented with Balsa for an Asynchronous Pipelined 8051 compatible Microcontroller,”  in Proc. International Computer Symposium (ICS’08), Taipei County, Taiwan, Nov. 13-15, 2008.
[31]	Chang-Jiu Chen, Wei-Min Cheng, Ruei-Fu Tsai, Hung-Yue Tsai, and Tuan-Chieh Wang, “A pipelined asynchronous 8051 soft-core imple-mented with Balsa,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS’08), Macao, China, Nov. 30-Dec. 3, 2008, pp. 976-979.
[32]	Yun-Zhu Xiang and Yue-Hua Ding, “Instruction Decoder Module Design of 32-bit RISC CPU Based on MIPS,” in Proc. Second International Conference on Genetic and Evolutionary Computing (WGEC’08), Huibei, China, Sept. 25-26, 2008, pp. 347-351.
[33]	Slo-Li Chu, Geng-Siao Li, and Chih-Nan Hsu, “Design a Fully MIPS32 ISA Processor with Corresponding Verification Environment,” in Proc. National Computer Symposium (NCS’09), Taipei, Taiwan, Nov. 27-28, 2009, pp. 288-299.
[34]	Hongkyun Jung, Hyoungjun Kim, Kwangmyoung Kang, and Kwangki Ryoo, “Performance Improvement and Low Power Design of Embedded Processor,” in Proc. International Conference on Convergence and hybrid Information Technology (ICCIT’08), vol. 2, Busan, Korea, Nov. 11-13, 2008, pp.140-145.
[35]	C51 Development Tools [Online]. Available: http://www.keil.com/c51/
[36]	OpenCores [Online]. Available: http://opencores.org/
[37]	Oregano Systems [Online]. Available: http://www.oregano.at/