隨著科技的進步人們對日常用品的需求提高，省電、體積小、價格低、功能多樣化的電子產品已成為趨勢，因此數位信號處理(Digital Signal Processing, DSP)與超大型積體電路(VLSI)之技術也隨之蓬勃發展，而在整個數位信號處理系統中，類比數位轉換器是影響系統效能的重要元件之一。
本論文主要是研究應用於高頻超音波之類比數位轉換器(Analog-to-DigitalConverter, ADC)。由於超音波有方便、無侵襲性、無放射性、影像易於取得等諸多特性，因此廣泛被應用於醫療上。相較於傳統醫療用超音波頻率範圍1~10MHz的超音波系統，高頻超音波（>20 MHz）將是未來的應用主軸，隨著頻率的上升，高頻超音波波長縮短，其空間解析度亦隨之提高，在中心頻率50 MHz的超音波影像系統中可達到約數十微米(μm)大小的空間解析度，因此相當適合用來觀察較微細的組織結構。類比數位轉換器是高頻超音波系統的重要零組件，為了實現高頻超音波系統前端，必須要有一個頻寬至少30MHz的類比數位轉換器，所以本研究計畫目標為設計實現一個10位元寬頻、多通道、低功耗三角積分類比數位轉換器，以應用於高頻超音波系統前端。

With the advancement of technology, people's demand for daily necessities has increased, and electronic products with low power consumption, small size, low price, and diversified functions have become a trend. Therefore, digital signal processing (DSP) and the technology of VLSI (very-large-scale integration) have also flourished, and analog digital converters are one of the important components that affect system performance throughout digital signal processing systems.
In this thesis we are mainly to study the analog-to-digital converter (ADC) applied to high-frequency ultrasonic systems. Ultrasonic waves are widely used in medical applications because of their convenience, non-invasiveness, non-radioactivity, and easy access to images. Compared with the traditional ultrasonic system with ultrasonic frequency range of 1~10MHz, high-frequency ultrasonic (>20MHz) will be the main application axis in the future. As the frequency increases, the high-frequency ultrasonic wavelength is shortened, and the spatial resolution is also followed. The spatial resolution of about ten micrometers (μm) can be achieved in an ultrasonic imaging system with a center frequency of 50 MHz, so it is quite suitable for observing a finer structure. The analog-to-digital converter is an important component of the high-frequency ultrasonic system. In order to realize the front end of the high-frequency ultrasonic system, an analog-to-digital converter with a bandwidth of at least 30 MHz must be used. Therefore, the goal of this research work is to design a 10-bit broadband and multi-frequency channel, low power delta-sigma analog-to-digital converter for high-frequency ultrasonic system front ends.

目錄
中文摘要 ............................................................................................................I
英文摘要 .......................................................................................................... II
內文目錄 ........................................................................................................ III
圖表目錄 ......................................................................................................... VI
第一章 概論 ..................................................................................................... 1
1.1 研究動機 .................................................................................................... 1
1.2 應用 ............................................................................................................ 3
1.3 論文架構 .................................................................................................... 4
第二章 三角積分調變器之基本原理 ............................................................. 5
2.1 三角積分調變器簡介 ................................................................................ 5
2.2 三角積分調變器架構 ................................................................................ 7
2.2.1單一迴路架構 ...................................................................................... 7
2.2.2多迴路架構 .......................................................................................... 8
2.3 量化器 ........................................................................................................ 9
2.3.1 量化誤差 ........................................................................................... 11
2.4 奈奎氏取樣定理 ...................................................................................... 13
2.5 超取樣技術 .............................................................................................. 14
2.6 雜訊移頻 .................................................................................................. 15
2.6.1 一階之雜訊移頻 ............................................................................... 17
2.6.2 二階之雜訊移頻 ............................................................................... 20
2.6.3 高階之雜訊移頻 ............................................................................... 21
第三章 連續時間三角積分調變器設計 ....................................................... 23
3.1 前言 .......................................................................................................... 23
3.2 轉換 DT DSM 至CT DSM .................................................................. 24
第四章 非理想效應分析 ............................................................................... 29
4.1 前言 .......................................................................................................... 29
4.2 運算放大器之非理想現象 ...................................................................... 29
4.2.1有限直流增益與係數偏移 ................................................................ 29
4.2.2有限增益與頻寬乘積 ........................................................................ 30
4.3比較器與DAC之非理想現象 ................................................................ 33
4.3.1迴授路徑的時間延遲(Excess loop delay) ........................................ 33
4.3.2比較器的磁滯現象 ............................................................................ 35
第五章 系統設計與電路設計 ....................................................................... 36
5.1 系統規格 .................................................................................................. 36
5.2 系統設計與模擬結果 .............................................................................. 36
5.2.1運算放大器之非理想模擬 ................................................................ 39
5.2.2比較器與DAC之非理想現象 .......................................................... 40
5.3系統設計與模擬結果 ............................................................................... 42
5.3.1運算放大器 ........................................................................................ 42
5.3.2共模迴授電路 .................................................................................... 43
5.3.3比較器 ................................................................................................ 44
5.3.4量化器 ................................................................................................ 44
5.3.5電流式DAC ....................................................................................... 46
5.3.6偏壓電路 ............................................................................................ 46
5.3.7模擬結果 ............................................................................................ 47
第六章 結論 ................................................................................................... 50
參考文獻 ......................................................................................................... 51
圖表目錄
圖目錄
圖1.1 各種ADC架構之應用範圍 ................................................................ 1
圖1.2 應用於醫療用手持式低功耗4D即時超音波系統架構 .................... 4
圖2.1 三角積分調變器區塊圖 ....................................................................... 5
圖2.2 三角積分調變器之架構 ....................................................................... 6
圖2.3 CIFB及CIFF架構 ............................................................................... 8
圖2.4 簡單之多級串接架構 ........................................................................... 8
圖2.5 MID-RISE量化和量化誤差 ............................................................... 10
圖2.6 MID-TREAD量化和量化誤差 .......................................................... 11
圖2.7 量化誤差之機率密度函數分布 ......................................................... 12
圖2.8 奈奎式取樣率之頻譜 ......................................................................... 13
圖2.9 超取樣轉換器之架構 ......................................................................... 14
圖2.10 經由低通濾波器後之功率頻譜密度 ............................................... 15
圖2.11 三角積分調變器之數學模型 ........................................................... 16
圖2.12 一階之三角積分調變器架構 ........................................................... 17
圖2.13 傳統二階三角積分調變器 ............................................................... 20
圖2.14 一階及二階雜訊移頻之功率頻譜密度 ........................................... 21
圖2.15 各種階數及OSR下之效能 ............................................................. 22
圖3.1 CT DSM 與DT DSM 開迴路模型 ................................................... 26
圖4.1 有限直流增益RC 積分器 ................................................................ 30
圖4.2 (A)考量次極點與增益誤差的二階DSM (B)修改之後的模型 (C)
最終的有限頻寬等效模型 ............................................................................. 32
圖4.3 使用NRZ 發生迴授延遲的情形 (A)理想波型 (B)發生延遲....... 34
圖4.4 使用RZ 發生迴授延遲的情形 (A)理想波型 (B)發生延遲 ......... 34
圖4.5 經過標準化發生迴授延遲的波形 ..................................................... 35
圖4.6 迴授路徑的時間延遲補償 ................................................................. 35
圖5.1 DT DSM 架構 ..................................................................................... 37
圖5.2 CT DSM 架構 ..................................................................................... 37
圖5.3 考慮迴路延遲時間補償之CT CIFB架構 ........................................ 38
圖5.4 MATLAB頻譜圖 ................................................................................ 39
圖5.5 有限直流增益OPAMP 模擬結果 .................................................... 39
圖5.6 有限增益與頻寬乘積模擬結果 ......................................................... 40
圖5.7 迴路延遲時間對系統效能的影響 ..................................................... 41
圖5.8 比較器遲滯 ......................................................................................... 41
圖5.9 整體電路圖 ......................................................................................... 42
圖5.10 疊接放大器 ....................................................................................... 42
圖5.11 疊接放大器波德圖 ........................................................................... 43
圖5.12 連續時間共模迴授電路 ................................................................... 43
圖5.13 比較器 ............................................................................................... 44
圖5.14 28-1 FLASH架構 ............................................................................... 45
圖5.15 電流式DAC ..................................................................................... 46
圖5.16 偏壓電路 ........................................................................................... 47
圖5.17三種製程變異參數TT SS FF的模擬結果 ...................................... 48
表目錄
表5.1 系統規格 ............................................................................................. 36
表5.2 系統系數表 ......................................................................................... 37
表5.3 系統系數表 ......................................................................................... 38
表5.4 結果表 ................................................................................................. 48
表5.5 結果比較表 ......................................................................................... 49

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