一.摘要
隨著半導體產業的發展IC的進步日新月異，藉由3D-IC的發展大幅減少了晶片的體積，3D-IC的成功主要仰賴於TSV的使用，TSV為直接貫穿晶片及晶圓的一種技術，藉此減少晶片與晶片之間的間隙，使晶片整體體積縮小，但在TSV製造過程中可能會產生填充不完全、中間有空隙亦或是填充過程中混入雜質等狀況發生，以及TSV的測試過程不容易，造成原因有以下幾點。
1)TSV大多埋沒在矽晶片裡面。
2)TSV的尺寸非常小，根據近期的文獻指出直徑多為10μm彼此的間距大約40μm。
3)一個3D-IC中的TSV數量龐大。
正因為以上原因，造成預接合測試中不容易對TSV進行檢測，特別是侵入式檢測方式，更是困難，因此我們選擇了現有非侵入之檢測方式，使用環形震盪器對TSV進行檢測並對其進行改良。
相較於其他檢測方法，使用環形震盪器有以下3點處。
1)此方法為非侵入式，不會對晶片造成外力傷害。
2)可以藉由更改電壓等等參數，達到更好的結果。
3)面積成本小
本篇文章致力於使用環形震盪器對TSV預接合測試，更正現有的錯誤模型[16]，使其更加貼近現實，並且改良現有的測試模型[18]，使其更加容易分辨錯誤，若其TSV發生開孔錯誤，則產生波形的頻率將會較正常情況快，另外可以藉由增加電壓的方式來大幅提升錯誤分辨率；若其TSV發生漏電流錯誤，則產生波形的頻率將會較正常情況快且震幅較正常情況小，另外可以藉由調整固定電壓來提升錯誤分辨率，此外，本篇文章的測試模型之測試所需時間與面積成本皆在適當範圍內，所增加的成本則在可以忽略的程度。

The popularity of 3D-IC is rising among industry and research groups. 3D-IC is based on Through Silicon Via (TSVs), which are emerging as one of the main competitors to continue the trend of Moore’s Law. We use ring oscillators to test TSV errors, and build some new ideas to that the existing fault model more realistic . If it gets a resistive-open fault, then the frequency of the wave will be faster than the normal one. After that, test resolution can be improved by increasing the voltage; if it gets a leakage fault, then the frequency of resulting wave will be faster, and the amplitude will be smaller than normal. In this case,, test resolution is increased by adjusting the particular voltage value. One other thing that worth to be mentioned is that the test time and cost area are within an appropriate range, thus the added cost is negligible in the test model required for this article

致謝                                           I
中文摘要                                      II
英文摘要                                      IV
大綱                                           V
圖片列表                                      VI
表格列表                                     VII

Chapter 1	緒論	                       1
1.1	研究背景與動機	                       1
1.2	論文簡介	                       5

Chapter 2	論文內運用的知識	       6
2.1	相關前期工作	                       6
2.2	現有錯誤模型	                       7

Chapter 3	論文硬體架構	              10
3.1 改良錯誤模型	                      10
3.2使用環形震盪器對TSV測試	              12

Chapter 4	實驗結果	              14
4.1	實驗結果說明	                      14
4.1.1	TSV開孔錯誤	                      14
4.1.2	TSV漏電流錯誤	                      18
4.1.3	結合TSV開孔錯誤與漏電流錯誤	      21
4.1.4	使用現有TSV開孔錯誤	              24
4.1.5	比較新TSV開孔與現有TSV開孔錯誤模型    25

Chapter 5	結論	                      26

圖片列表

圖 1.1 3D-IC多塔示意圖[3]	               1
圖 1.2 使用環形震盪器對TSV測試[16]	       4
圖 2.1 對照現實狀況及錯誤模型	               9
圖 3.1 我們所使用的錯誤模型	              11
圖 3.2 使用環形震盪器對TSV測試示意圖	      11
圖 3.3 若發生錯誤其頻率都將快於正常的TSV      13
圖 4.1 c=331fF、200fF、100fF 0.6v	      15 
圖 4.2 c=331fF、200fF、100fF 0.6v	      15
圖 4.3 增加電壓增加其錯誤分辨率	              17
圖 4.4 比較無錯誤、1K漏電流錯誤、6K漏電流錯誤 19
圖 4.5 在特定電壓下其錯誤分辨明顯	      20
圖 4.6 比較同時發生開孔錯誤及漏電流錯誤       22
圖 4.7 增加電壓同樣可以增加錯誤分辨率	      23
圖 4.8 現有開孔錯誤模型	                      24
圖 4.9 比較新開孔與現有開孔錯誤模型	      25

 
表格列表

表 4.1 比較不同電壓的頻率變化	              16

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