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系統識別號 U0002-0107200511394000
中文論文名稱 使用雙迴授路徑組成之鎖相迴路設計製作
英文論文名稱 Design and Implementation of Dual-Feedback Phase-Locked Loop
校院名稱 淡江大學
系所名稱(中) 電機工程學系碩士班
系所名稱(英) Department of Electrical Engineering
學年度 93
學期 2
出版年 94
研究生中文姓名 史義順
研究生英文姓名 Yi-Shun Shih
電子信箱 ysshih@ee.tku.edu.tw
學號 692390403
學位類別 碩士
語文別 英文
口試日期 2005-06-09
論文頁數 60頁
口試委員 指導教授-郭建宏
委員-黃育賢
委員-陳建中
委員-陳淳杰
委員-江正雄
中文關鍵字 相位頻率偵測器  電荷幫浦  迴路濾波器  除頻器  死區  劇跳 
英文關鍵字 Phase Frequency Detector (PFD)  Charge Pump(CP)  Loop Filter  Frequency Divider (FD)  Dead Zone  Jitter 
學科別分類 學科別應用科學電機及電子
中文摘要 在現今無線通訊上,例如:無線區域網路(WLANs)、行動電話及衛星通訊設備…等等,鎖相迴路(Phase Locked Loop,PLL)常扮演著重要的角色。鎖相迴路的功能在於鎖定相位,可以使電路的時脈同步並減少非理想效應所產生的偏差。由於製程的演進及科技的進步,使目前晶片的操作速度越來越快,然而晶片內部的非理想效應會使相位產生偏差延遲,導致所需的資料結果產生錯誤。這時鎖相迴路就可以用來校正減低延遲的時間以確保資料的正確性。

在應用上,鎖相迴路在外部輸入較低振盪時脈經由內部時脈合成的功能可以產生一個高速時脈的輸出。而在時脈合成的過程中,穩定時間(Settling Time)與壓控震盪器控制線上的漣波(Ripple)大小常有相當重要的取捨。對於頻率合成器而言,穩定時間對於通道切換的速度有著重要的影響,而壓控震盪器控制線上的漣波則關係著頻率合成器的輸出是否為一穩定的時脈。而如何設計出擁有較快穩定時間及具有穩定的時脈輸出的鎖相迴路是本論文所探討的重點。

本論文主題在於使用標準互補式金氧半製程,實現一個有雙回授路徑組成之鎖相迴路。論文內容可以兩個部份,第一部份在第二章,其中分別描述鎖相迴路的原理和分析鎖相迴路整個系統。第三章和第四章為第二部份,敘述了鎖相迴路的電路設計、製作及量測。最後,將在第五章裡做總結。
英文摘要 Phase-locked-loops (PLLs) are widely used in wireless data telecommunications, such as wireless local area networks (WLANs), mobile and satellite communications. In these applications, the PLLs are usually used as a clock synthesis block to generate a high-speed internal clock from an external fixed oscillation source.

There is a tight tradeoff between the settling time and the amplitude of the ripple on the VCO control line in the design of phase-locked loops. This tradeoff for phase-locked RF synthesizers limits the performance in terms of the channel switching speed and the magnitude of the reference sidebands that appear at the output.

This paper presents a double PFDs PLL approach with a tunable delay unit to produce a small ripple on the VCO control line as well as a low jitter performance metric. Besides, the proposed architecture also provide another benefit that less settling time is required compared to the architecture with only one PFD.

Section II develops the fundamental principle for the architecture of the proposed phase-locked loop. The circuit design and simulation results of the presented phase-locked loop are shown in Section III and Section IV, respectively. Finally, a conclusion is given in Section V.
論文目次 Table of Contents
Chapter 1: Introduction 1
1.1 Motivation 1
1.2 Thesis Overview 2
Chapter 2: The Principles of Phase-Locked Loop 4
2.1 PLL Fundamentals 4
2.1.1 PLL Linear Model 6
2.1.2 Phase Frequency Detector (PFD) 7
2.1.3 Charge Pump (CP) 9
2.1.4 Closed-Loop Analysis  12
2.1.5 3rd PLL 14
2.1.6 Noise Trade-offs in PLL design 17
2.1.7 Voltage-controlled Oscillator 19
2.1.8 Frequency Divider 22
2.2 System Simulation 22
Chapter 3: Design and Implementation of Dual-feedback
Phase-Locked Loop 25
3.1 Introduction 25
3.2 Phase-Locked Loop Overview 26
3.3 The Proposed PLL Structure and Operation
Principles 27
3.3.1 Two PFD with Separate Dead zones 29
3.3.2 The Operations of The Proposed PLL
Architecture 31
3.4 Circuit Implementation 33
3.4.1 Phase Frequency Detector (PFD) 33
3.4.2 Charge Pump (CP) 34
3.4.3 Loop Filter (LF) 37
3.4.4 Voltage-controlled-oscillator (VCO) 39
3.4.5 Frequency Divider (FD) 41
3.5 Simulation Results and Layout 42
Chapter 4: Measurement Results 46
4.1 Measurement Setup and Measurement Results 46
Chapter 5: Conclusions 57
References 58

List of Figures
Figure 2.1 The charge pump PLL block diagram 5
Figure 2.2 State diagram of PFD 7
Figure 2.3 PFD response with (a) A lagging B,
(b) ωA > ωB 8
Figure 2.4 PFD characteristic 9
Figure 2.5 Block diagram of PFD with charge pump,
and the timing diagram 10
Figure 2.6 Addition of a zero to a charge pump 11
Figure 2.7 Linear model of a PLL-based frequency
synthesizer 12
Figure 2.8 First-order loop filter and the
corresponding open-loop response 13
Figure 2.9 Second-order loop filter and the
corresponding open-loop response 14
Figure 2.10 Block diagram of a typical PLL 17
Figure 2.11 Definition of a VCO 19
Figure 2.12 Differential pair with variable output
time constant [23] 21
Figure 2.13 The PLL behavior model by Simulink 24
Figure 3.1 PLL function block diagram 26
Figure 3.2 A conventional PLL architecture 28
Figure 3.3 The proposed PLL architecture with
double PFDs scheme 28
Figure 3.4 Two PFDs with separate dead zones 30
Figure 3.5 The combination of two PFDs 31
Figure 3.6 The operations of the proposed PLL
architecture. (a) Signal definitions
in two PFDs. (b) F lagging R1 and R2.
(c) F leading R1 and R2.
(d) F falling into the space between
R1 and R2 32
Figure 3.7 The conventional PFD circuit 33
Figure 3.8 (a)The schematic of three-state PFD
with delay buffers (b) truth table 34
Figure 3.9 Charge pump circuit 35
Figure 3.10 Clock feedthrough effect 35
Figure 3.11 Switch circuit of the charge pump 36
Figure 3.12 PFD, CP and LF interaction 36
Figure 3.13 A second order passive loop filter [34] 37
Figure 3.14 The schematics of (a) the delay cell and
(b) the ring oscillator 40
Figure 3.15 Operating frequency versus control voltage
for the ring oscillator 41
Figure 3.16 The TSPC D flip-flop circuit 41
Figure 3.17 Layout view of the proposed PLL 42
Figure 3.18 Simulation results of the proposed PLL, when
(a) Δt = 125ps (b) Δt = 80ps 43
Figure 3.19 Output frequencies when PLL is locked 43
Figure 3.20 Transient responses of the PLLs 44
Figure 3.21 The simulink of the double-PFD PLL 45
Figure 4.1 Chip micrograph 46
Figure 4.2 PCB 46
Figure 4.3 Measurement setup 47
Figure 4.4 Phase delay is 125ps 48
Figure 4.5 Measured PLL feedback signal frequency is
62.5MHz, which is divided by 16 from the VCO
oscillation frequency 1GHz. 48
Figure 4.6 The locked state of PLL when phase delay
is 125ps 49
Figure 4.7 Phase delay is 80ps 50
Figure 4.8 The measured frequency is 62.5MHz when the
phase delay is 80ps 50
Figure 4.9 The locked state of PLL when phase delay is
80ps 51
Figure 4.10 The measured parameters of the feedback
signal 51
Figure 4.11 Jitter histogram of PLL at 62.5MHz when phase
delay is 125ps 52
Figure 4.12 Jitter histogram of PLL at 62.5MHz when phase
delay is 80ps 53
Figure 4.13 The PLL output frequency 53
Figure 4.14 Output spectrum of PLL span 1MHz 55
Figure 4.15 Output spectrum of PLL span 100MHz 55
Figure 4.16 Phase noise plot for the proposed PLL 56

List of Tables
Table 2.1 Relationship between γ and PM 16
Table 3.1 Performace Summary of the Proposed PLL 44
Table 4.1 Summary of measured PLL performance 56
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